56 lines
2.0 KiB
C
56 lines
2.0 KiB
C
#include "iwdg.h"
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#include "stm32f4xx_iwdg.h"
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//////////////////////////////////////////////////////////////////////////////////
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//This program is for educational purposes only, without the author's permission, may not be used for any other purpose
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//ALIENTEK STM32F407 Development Board
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//Independent watch-dog driver code
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//Hot Atomic @ALIENTEK
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//Forum: www.openedv.com
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//Date created: 2015/9/1
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//Version: V1.0
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//All rights reserved pirated reserved.
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//Copyright(C) Guangzhou wing electronic technology limited company 2014-2024
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//All rights reserved
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//////////////////////////////////////////////////////////////////////////////////
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//Initialize watch-dog
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void IWDG_Init(void)
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{
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/* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency
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dispersion) */
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/* Enable write access to IWDG_PR and IWDG_RLR registers */
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IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
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/* IWDG counter clock: 40KHz(LSI) / 128 = 312.5 Hz : 3.2ms */
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/* 0.8ms ~ 3276.8ms */
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// IWDG_Prescaler_4, 0, 0.1, 409.6
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// IWDG_Prescaler_8, 1, 0.2, 819.2
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// IWDG_Prescaler_16, 2, 0.4, 1638.4
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// IWDG_Prescaler_32, 3, 0.8, 3276.8
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// IWDG_Prescaler_64, 4, 1.6, 6553.6
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// IWDG_Prescaler_128 5, 3.2, 13107.2
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// IWDG_Prescaler_256 6, 6.4, 26214.4
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/* IWDG counter clock: LSI/128 */
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IWDG_SetPrescaler(IWDG_Prescaler_128);
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/* Set counter reload value to obtain 250ms IWDG TimeOut.
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Counter Reload Value = 1000ms / IWDG counter clock period
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= 1000ms / (LSI/128)
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=
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Counter Reload Value = 250ms/IWDG counter clock period
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= 250ms / (LSI/32)
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= 0.25s / (LsiFreq/32)
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= LsiFreq/(32 * 4)
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= LsiFreq/128
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*/
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IWDG_SetReload(1000);
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/* Reload IWDG counter */
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IWDG_ReloadCounter();
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/* Enable IWDG (the LSI oscillator will be enabled by hardware) */
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IWDG_Enable();
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}
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