#include "iwdg.h"
#include "stm32f4xx_iwdg.h"
//////////////////////////////////////////////////////////////////////////////////	 
//This program is for educational purposes only, without the author's permission, may not be used for any other purpose
//ALIENTEK STM32F407 Development Board
//Independent watch-dog driver code	   
//Hot Atomic @ALIENTEK
//Forum: www.openedv.com
//Date created: 2015/9/1
//Version: V1.0
//All rights reserved pirated reserved.
//Copyright(C) Guangzhou wing electronic technology limited company 2014-2024
//All rights reserved									  
////////////////////////////////////////////////////////////////////////////////// 	

//Initialize watch-dog
void IWDG_Init(void)
{
    /* IWDG timeout equal to 250 ms (the timeout may varies due to LSI frequency
     dispersion) */
    /* Enable write access to IWDG_PR and IWDG_RLR registers */
    IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
    
    /* IWDG counter clock: 40KHz(LSI) / 128 = 312.5 Hz : 3.2ms */
    /* 0.8ms ~ 3276.8ms */
    // IWDG_Prescaler_4,  0, 0.1,   409.6 
    // IWDG_Prescaler_8,  1, 0.2,   819.2 
    // IWDG_Prescaler_16, 2, 0.4,  1638.4 
    // IWDG_Prescaler_32, 3, 0.8,  3276.8 
    // IWDG_Prescaler_64, 4, 1.6,  6553.6 
    // IWDG_Prescaler_128 5, 3.2, 13107.2 
    // IWDG_Prescaler_256 6, 6.4, 26214.4 

    /* IWDG counter clock: LSI/128 */
    IWDG_SetPrescaler(IWDG_Prescaler_128);
    
    /* Set counter reload value to obtain 250ms IWDG TimeOut.
     Counter Reload Value = 1000ms / IWDG counter clock period 
                          = 1000ms / (LSI/128)
                          = 
    
     Counter Reload Value = 250ms/IWDG counter clock period 
                          = 250ms / (LSI/32)
                          = 0.25s / (LsiFreq/32)
                          = LsiFreq/(32 * 4)
                          = LsiFreq/128
    */
    IWDG_SetReload(1000);
    
    /* Reload IWDG counter */
    IWDG_ReloadCounter();
    
    /* Enable IWDG (the LSI oscillator will be enabled by hardware) */
    IWDG_Enable();
}