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Backup before error handling refactoring

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This commit is contained in:
jkwoo
2026-07-13 17:10:02 +09:00
commit 04fc19b485
1132 changed files with 347840 additions and 0 deletions
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40
.clangd Normal file
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CompileFlags:
Add:
- -ferror-limit=0
- -Wno-invalid-command-line-argument
- -Wno-unknown-argument
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/USER"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/APP"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/SYSTEM"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/HARDWARE"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/CORE"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/FWLIB/inc"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/UCOSIII/uCOS_CONFIG"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/UCOSIII/uCOS-III/Source"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/UCOSIII/uC-CPU"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/UCOSIII/uC-CPU/ARM-Cortex-M3/RealView"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/UCOSIII/uC-LIB"
- -I"d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/UCOSIII/uCOS-III/Ports/ARM-Cortex-M3/Generic/RealView"
- -D"USE_STDPERIPH_DRIVER"
- -D"STM32F10X_MD"
- -D"__GNUC__=4"
- -std=c99
- "-include"
- "d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/USER/stm32f10x.h"
Remove:
- -O*
- -g
- --apcs=interwork
- --cpu
- Cortex-M3
- --li
- --split_sections
- --c99
- --no_depend_system_headers
- --depend*
- --diag_suppress*
CompilationDatabase: d:/Project/Firmware/PR/BMU/PR-67150/App/BMU_21S_APP_V1003_AG/USER/build/BMU_21S_APP
Diagnostics:
UnusedIncludes: None
Suppress: ["drv_unknown_argument", "invalid-command-line-argument", "unknown-argument"]

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.editorconfig Normal file
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root = true
[*]
indent_style = space
indent_size = 4
tab_width = 4
end_of_line = lf
charset = utf-8
trim_trailing_whitespace = true
insert_final_newline = true
[*.{c,h}]
indent_style = tab
indent_size = 4
tab_width = 4

590
APP/alarm.c Normal file
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/* Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* High Level description:
* http://www.ti.com/lit/ds/symlink/bq28400.pdf
* Thechnical Reference:
* http://www.ti.com/lit/ug/sluu431/sluu431.pdf
*/
#include "includes.h"
#include "dflash_sf1.h"
#include "device_param.h"
#include "asutil.h"
#include "console.h"
#include "temp.h"
#include "led.h"
u8 SleepMode = false;
u32 smode_tick = 60 * 1000;
u32 CV_Diff_Time = 60 * 1000;
void dec_sleepmode_time(u32 tick);
void dec_cv_diff_time(u32 tick);
void ProcessSafety_COV(void);
void ProcessSafety_CUV(void);
void ProcessSafety_OTA(void);
void ProcessSafety_LTA(void);
void ProcessSafety_CellVoltageDiff(void);
void ProcessStatusCheck(void);
void ProcessSafetyControl(void);
#define SLEEP_VOLTAGE 4200
#define WAKEUP_VOLTAGE 4500
#define SLEEP_MODE_TIME 60 * 1000
#define CELL_DEVIATION_CHECK_VOLTAGE 4500
void dec_alarm_tick(u32 tick)
{
dec_cv_diff_time(tick);
dec_sleepmode_time(tick);
}
void dec_sleepmode_time(u32 tick)
{
if (smode_tick > 0)
{
if (smode_tick > tick)
smode_tick -= tick;
else
smode_tick = 0;
}
}
u8 GetSleepMode(void)
{
return SleepMode;
}
void SetSleepMode(u8 mode)
{
SleepMode = mode;
}
void CheckSleepMode(void)
{
if (SleepMode == true)
{
if (device_status.op_status == 1)
{
SleepMode = false;
smode_tick = SLEEP_MODE_TIME;
}
}
else
{
if ((device_status.protection.bit.cell_under_voltage) || (device_status.protection.bit.under_voltage))
{
if (smode_tick == 0)
SleepMode = true;
}
else
{
smode_tick = SLEEP_MODE_TIME;
}
}
}
void ProcessAlarm(void)
{
if (device_status.battery_status.bit.INIT) {
device_status.protection.bit.afe_fail = device_status.battery_status.bit.AFE;
if (device_status.battery_status.bit.AFE == false){
ProcessSafety_COV();
ProcessSafety_CUV();
}
ProcessSafety_OTA();
ProcessSafety_LTA();
ProcessSafety_CellVoltageDiff();
CheckSleepMode();
}
ProcessStatusCheck();
ProcessSafetyControl();
}
void ProcessSafety_COV(void)
{
/* Cell Over Voltage Check */
for (int i = 0; i < CellQty; i++) {
/* Cell Over Voltage Protection */
if (device_status.cov_protection_cell.uValue & BIT32(i)) {
// Release check
if (device_value.Cell.voltage[i] < (device_param.safety.voltage.COV_Recovery * 10))
device_status.cov_protection_cell.uValue &= ~BIT32(i);
} else {
// Alarm check
if (device_value.Cell.voltage[i] > (device_param.safety.voltage.COV_Threshold * 10))
device_status.cov_protection_cell.uValue |= BIT32(i);
}
/* Cell Over Voltage Warning */
if (device_status.cov_warning_cell.uValue & BIT32(i)) {
// Release check
if (device_value.Cell.voltage[i] < (device_param.safety.voltage.COV_Recovery * 10))
device_status.cov_warning_cell.uValue &= ~BIT32(i);
} else {
// Alarm check
if (device_value.Cell.voltage[i] > (device_param.safety.voltage.COV_Warning * 10))
device_status.cov_warning_cell.uValue |= BIT32(i);
}
}
if (device_status.cov_protection_cell.uValue != 0) {
device_status.protection.bit.cell_over_voltage = true;
} else {
device_status.protection.bit.cell_over_voltage = false;
}
if (device_status.cov_warning_cell.uValue != 0) {
device_status.warning.bit.cell_over_voltage = true;
} else {
device_status.warning.bit.cell_over_voltage = false;
}
/* System Over charge protection */
if (device_status.protection.bit.over_voltage)
{
// Release check
if (device_value.BatVoltage < device_param.safety.voltage.SOV_Recovery)
device_status.protection.bit.over_voltage = false;
}
else
{
// Alarm check
if (device_value.BatVoltage > device_param.safety.voltage.SOV_Threshold)
device_status.protection.bit.over_voltage = true;
}
/* System Over Voltage Warning */
if (device_status.warning.bit.over_voltage)
{
// Release check
if (device_value.BatVoltage < device_param.safety.voltage.SOV_Recovery)
device_status.warning.bit.over_voltage = false;
} else {
// Alarm check
if (device_value.BatVoltage > device_param.safety.voltage.SOV_Warning)
device_status.warning.bit.over_voltage = true;
}
}
void ProcessSafety_CUV(void)
{
/* Cell under voltage check */
for (int i = 0; i < CellQty; i++)
{
/* Cell under voltage protection */
if (device_status.cuv_protection_cell.uValue & BIT32(i))
{
// Recovery Check
if (device_value.Cell.voltage[i] > (device_param.safety.voltage.CUV_Recovery * 10))
device_status.cuv_protection_cell.uValue &= ~BIT32(i);
}
else
{
// Protection Check
if (device_value.Cell.voltage[i] < (device_param.safety.voltage.CUV_Threshold * 10))
device_status.cuv_protection_cell.uValue |= BIT32(i);
}
/* Cell under voltage warning */
if (device_status.cuv_warning_cell.uValue & BIT32(i))
{
// Recovery Check
if (device_value.Cell.voltage[i] > (device_param.safety.voltage.CUV_Recovery * 10))
device_status.cuv_warning_cell.uValue &= ~BIT32(i);
}
else
{
// Warning Check
if (device_value.Cell.voltage[i] < (device_param.safety.voltage.CUV_Warning * 10))
device_status.cuv_warning_cell.uValue |= BIT32(i);
}
}
if (device_status.cuv_protection_cell.uValue != 0)
device_status.protection.bit.cell_under_voltage = true;
else
device_status.protection.bit.cell_under_voltage = false;
if (device_status.cuv_warning_cell.uValue != 0)
device_status.warning.bit.cell_under_voltage = true;
else
device_status.warning.bit.cell_under_voltage = false;
if (device_status.protection.bit.cell_under_voltage)
{
if (device_status.op_status == 0x0001)
{
device_status.protection.bit.cell_under_voltage = 0;
device_status.cuv_protection_cell.uValue = 0;
}
}
/* System under voltage protection */
if (device_status.protection.bit.under_voltage)
{
// Release check
if (device_value.BatVoltage > device_param.safety.voltage.SUV_Recovery)
device_status.protection.bit.under_voltage = false;
}
else
{
// Alarm check
if (device_value.BatVoltage < device_param.safety.voltage.SUV_Threshold)
device_status.protection.bit.under_voltage = true;
}
/* System under voltage warning */
if (device_status.warning.bit.under_voltage)
{
// Release check
if (device_value.BatVoltage > device_param.safety.voltage.SUV_Recovery)
device_status.warning.bit.under_voltage = false;
}
else
{
// Alarm check
if (device_value.BatVoltage < device_param.safety.voltage.SUV_Warning)
device_status.warning.bit.under_voltage = true;
}
if (device_status.protection.bit.under_voltage)
{
if (device_status.op_status == 0x0001)
{
device_status.protection.bit.under_voltage = 0;
}
}
}
void ProcessSafety_OTA(void)
{
/* Charge High Temperature */
for (int i = 0; i < TempQty; i++)
{
if (ADState(i) != AD_FAIL)
{
s16 aTemp = device_value.Temp.temperature[i];
/* Over Temperature Charge Protection */
if (device_status.otc_protection_temp.uValue & BIT(i))
{
// Recovery Check
if (aTemp < device_param.safety.temperature.OT_Chg_Recovery)
device_status.otc_protection_temp.uValue &= ~BIT(i);
}
else
{
// Protection Check, when charging
if (device_status.battery_status.bit.MD == 0)
{
if (aTemp > device_param.safety.temperature.OT_Chg_Threshold)
device_status.otc_protection_temp.uValue |= BIT(i);
}
}
/* Over Temperature Charge Warning */
if (device_status.otc_warning_temp.uValue & BIT(i))
{
// Recovery Check
if (aTemp < device_param.safety.temperature.OT_Chg_Recovery)
device_status.otc_warning_temp.uValue &= ~BIT(i);
}
else
{
// Warning Check, when charging
if (device_status.battery_status.bit.MD == 0)
{
if (aTemp > device_param.safety.temperature.OT_Chg_Warning)
device_status.otc_warning_temp.uValue |= BIT(i);
}
}
}
}
/* OTC Protection */
if (device_status.otc_protection_temp.uValue != 0)
device_status.protection.bit.chg_high_temp = true;
else
device_status.protection.bit.chg_high_temp = false;
/* OTC Warning */
if (device_status.otc_warning_temp.uValue != 0)
device_status.warning.bit.chg_high_temp = true;
else
device_status.warning.bit.chg_high_temp = false;
/* High Temperature Discharge */
for (int i = 0; i < TempQty; i++)
{
if (ADState(i) != AD_FAIL)
{
s16 aTemp = device_value.Temp.temperature[i];
/* Over Temperature Discharge Protection */
if (device_status.otd_protection_temp.uValue & BIT(i))
{
// Recovery Check
if (aTemp < device_param.safety.temperature.OT_Dsg_Recovery)
device_status.otd_protection_temp.uValue &= ~BIT(i);
}
else
{
// Protection Check, when charging
if (device_status.battery_status.bit.MD == 1)
{
if (aTemp > device_param.safety.temperature.OT_Dsg_Threshold)
device_status.otd_protection_temp.uValue |= BIT(i);
}
}
/* Over Temperature Charge Warning */
if (device_status.otd_warning_temp.uValue & BIT(i))
{
// Recovery Check
if (aTemp < device_param.safety.temperature.OT_Dsg_Recovery)
device_status.otd_warning_temp.uValue &= ~BIT(i);
}
else
{
// Warning Check, when charging
if (device_status.battery_status.bit.MD == 1)
{
if (aTemp > device_param.safety.temperature.OT_Dsg_Warning)
device_status.otd_warning_temp.uValue |= BIT(i);
}
}
}
}
/* OTD Protection */
if (device_status.otd_protection_temp.uValue != 0)
device_status.protection.bit.dsg_high_temp = true;
else
device_status.protection.bit.dsg_high_temp = false;
/* OTD Warning */
if (device_status.otd_warning_temp.uValue != 0)
device_status.warning.bit.dsg_high_temp = true;
else
device_status.warning.bit.dsg_high_temp = false;
}
void ProcessSafety_LTA(void)
{
/* Charge Low Temperature */
for (int i = 0; i < TempQty; i++)
{
if (ADState(i) != AD_FAIL)
{
s16 aTemp = device_value.Temp.temperature[i];
/* Over Temperature Charge Protection */
if (device_status.ltc_protection_temp.uValue & BIT(i))
{
// Recovery Check
if (aTemp > device_param.safety.temperature.LT_Chg_Recovery)
device_status.ltc_protection_temp.uValue &= ~BIT(i);
}
else
{
// Protection Check, when charging
if (device_status.battery_status.bit.MD == 0)
{
if (aTemp < device_param.safety.temperature.LT_Chg_Threshold)
device_status.ltc_protection_temp.uValue |= BIT(i);
}
}
/* Low Temperature Charge Warning */
if (device_status.ltc_warning_temp.uValue & BIT(i))
{
// Recovery Check
if (aTemp > device_param.safety.temperature.LT_Chg_Recovery)
device_status.ltc_warning_temp.uValue &= ~BIT(i);
}
else
{
// Warning Check, when charging
if (device_status.battery_status.bit.MD == 0)
{
if (aTemp < device_param.safety.temperature.LT_Chg_Warning)
device_status.ltc_warning_temp.uValue |= BIT(i);
}
}
}
}
/* LTC Protection */
if (device_status.ltc_protection_temp.uValue != 0)
device_status.protection.bit.chg_low_temp = true;
else
device_status.protection.bit.chg_low_temp = false;
/* LTC Warning */
if (device_status.ltc_warning_temp.uValue != 0)
device_status.warning.bit.chg_low_temp = true;
else
device_status.warning.bit.chg_low_temp = false;
/* Low Temperature Discharge */
for (int i = 0; i < DEVICE_MAX_TEMP; i++)
{
if (ADState(i) != AD_FAIL)
{
s16 aTemp = device_value.Temp.temperature[i];
/* Low Temperature Discharge Protection */
if (device_status.ltd_protection_temp.uValue & BIT(i))
{
// Recovery Check
if (aTemp > device_param.safety.temperature.LT_Dsg_Recovery)
device_status.ltd_protection_temp.uValue &= ~BIT(i);
}
else
{
// Protection Check, when charging
if (device_status.battery_status.bit.MD == 1)
{
if (aTemp < device_param.safety.temperature.LT_Dsg_Threshold)
device_status.ltd_protection_temp.uValue |= BIT(i);
}
}
/* Over Temperature Charge Warning */
if (device_status.ltd_warning_temp.uValue & BIT(i))
{
// Recovery Check
if (aTemp > device_param.safety.temperature.LT_Dsg_Recovery)
device_status.ltd_warning_temp.uValue &= ~BIT(i);
}
else
{
// Warning Check, when charging
if (device_status.battery_status.bit.MD == 1)
{
if (aTemp < device_param.safety.temperature.LT_Dsg_Warning)
device_status.ltd_warning_temp.uValue |= BIT(i);
}
}
}
}
/* LTD Protection */
if (device_status.ltd_protection_temp.uValue != 0)
device_status.protection.bit.dsg_low_temp = true;
else
device_status.protection.bit.dsg_low_temp = false;
/* LTD Warning */
if (device_status.ltd_warning_temp.uValue != 0)
device_status.warning.bit.dsg_low_temp = true;
else
device_status.warning.bit.dsg_low_temp = false;
}
void dec_cv_diff_time(u32 tick)
{
if (CV_Diff_Time > tick)
CV_Diff_Time -= tick;
else
CV_Diff_Time = 0;
}
void ProcessSafety_CellVoltageDiff(void)
{
if (device_value.BatVoltage >= CELL_DEVIATION_CHECK_VOLTAGE)
{
/* Cell Voltage Diff warning */
if (device_status.warning.bit.cell_voltage_diff)
{
// release check
if (device_value.Cell.avg.diff < (device_param.safety.cv_diff.Cell_Voltage_Diff_Recovery * 10))
device_status.warning.bit.cell_voltage_diff = false;
}
else
{
// alarm check
if (device_value.Cell.avg.diff > (device_param.safety.cv_diff.Cell_Voltage_Diff_Warning * 10))
device_status.warning.bit.cell_voltage_diff = true;
}
/* Cell Voltage Diff protection */
if (device_status.protection.bit.cell_voltage_diff)
{
// release check
if (device_value.Cell.avg.diff < (device_param.safety.cv_diff.Cell_Voltage_Diff_Recovery * 10))
{
device_status.protection.bit.cell_voltage_diff = false;
}
}
else
{
// alarm check
if (device_value.Cell.avg.diff > (device_param.safety.cv_diff.Cell_Voltage_Diff_Threshold * 10))
{
if (CV_Diff_Time == 0)
device_status.protection.bit.cell_voltage_diff = true;
}
else
{
CV_Diff_Time = device_param.safety.cv_diff.Cell_Voltage_Diff_Time * 1000;
}
}
}
else
{
device_status.warning.bit.cell_voltage_diff = 0;
}
}
void ProcessStatusCheck(void)
{
// Alarm Status
if (device_status.battery_status.bit.INIT == false)
device_status.alarm_status = 0x0003; // Warming Up
else if (device_status.protection.value != 0)
device_status.alarm_status = 0x0002; // Protection
else if (device_status.warning.value != 0)
device_status.alarm_status = 0x0001; // Warning
else
device_status.alarm_status = 0x0000; // Normal
}
#define SFC_CELL_VOLTAGE_MAX 39500
#define SFC_CELL_VOLTAGE_MIN 18000
#define SFC_TEMP_MAX 900
void ProcessSafetyControl(void)
{
u8 flag = false;
for (int i = 0; i < CellQty; i++) {
if (device_value.Cell.voltage[i] > SFC_CELL_VOLTAGE_MAX) { flag = true; break; }
if (device_value.Cell.voltage[i] < SFC_CELL_VOLTAGE_MIN) { flag = true; break; }
}
if (flag == false) {
for (int i = 0; i < TempQty; i++) {
if (device_value.Temp.temperature[i] > SFC_TEMP_MAX) { flag = true; break; }
}
}
if (flag) {
SAFETY_SIGNAL = 1;
} else {
SAFETY_SIGNAL = 0;
}
}

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APP/alarm.h Normal file
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/*****************************************************************************
*
* File : alarm.h
* Compiler : IAR C 6.30
* Revision : $Revision: 1.0 $
* Date : $Date: 2015 / 03 / 13
* Updated by : $Author: Jongkwang Woo
*
* Support mail : spirit0305@naver.com
*
* Description : Header file for alarm.c
*
****************************************************************************/
#ifndef _ALARM_H_
#define _ALARM_H_
#include <stm32f10x.h>
void ProcessAlarm(void);
void dec_alarm_tick(u32 tick);
u8 GetSleepMode(void);
void SetSleepMode(u8 mode);
#endif

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/**
******************************************************************************
* File Name : app_ver.c
* Description : This file provides code for application version
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2024 Amogreentech Co., Ltd.
* All rights reserved.</center></h2>
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include <includes.h>
#include <string.h>
#include "app_ver.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define APP_VER_CRITICAL 1
#define APP_VER_MAJOR 0
#define APP_VER_MINOR 0
#define APP_VER_COMPILE 5
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototype -----------------------------------------------*/
/* Private function ----------------------------------------------------------*/
void GetAppVersion(u8 *ver)
{
ver[0] = APP_VER_CRITICAL;
ver[1] = APP_VER_MAJOR;
ver[2] = APP_VER_MINOR;
ver[3] = APP_VER_COMPILE;
}
#ifdef CONSOLE_DEBUG
void APPVerDisplay(void)
{
u8 ver[4];
GetAppVersion(ver);
printf(" %s [OPERATING] VER %d.%d.%d.%d [%s %s]",
BD_MODEL,
ver[0],
ver[1],
ver[2],
ver[3],
__DATE__,
__TIME__
);
}
u16 GetAppVersionStr(u8 *vStr)
{
sprintf((char *)vStr, "%d.%d.%d.%d",
APP_VER_CRITICAL,
APP_VER_MAJOR,
APP_VER_MINOR,
APP_VER_COMPILE
);
return strlen((char *)vStr);
}
void GET_BUILD_DATETIME(u8 *datetime)
{
u8 date_str[12];
u8 time_str[12];
sprintf((char *)date_str, "%s", __DATE__);
sprintf((char *)time_str, "%s", __TIME__);
memcpy(&datetime[0], &date_str[7], 4); //year
if (memcmp(&date_str[0], "Jan", 3) == 0) //month
memcpy(&datetime[4], "01", 2);
else if (memcmp(&date_str[0], "Feb", 3) == 0)
memcpy(&datetime[4], "02", 2);
else if (memcmp(&date_str[0], "Mar", 3) == 0)
memcpy(&datetime[4], "03", 2);
else if (memcmp(&date_str[0], "Apr", 3) == 0)
memcpy(&datetime[4], "04", 2);
else if (memcmp(&date_str[0], "May", 3) == 0)
memcpy(&datetime[4], "05", 2);
else if (memcmp(&date_str[0], "Jun", 3) == 0)
memcpy(&datetime[4], "06", 2);
else if (memcmp(&date_str[0], "Jul", 3) == 0)
memcpy(&datetime[4], "07", 2);
else if (memcmp(&date_str[0], "Aug", 3) == 0)
memcpy(&datetime[4], "08", 2);
else if (memcmp(&date_str[0], "Sep", 3) == 0)
memcpy(&datetime[4], "09", 2);
else if (memcmp(&date_str[0], "Oct", 3) == 0)
memcpy(&datetime[4], "10", 2);
else if (memcmp(&date_str[0], "Nov", 3) == 0)
memcpy(&datetime[4], "11", 2);
else if (memcmp(&date_str[0], "Dec", 3) == 0)
memcpy(&datetime[4], "12", 2);
memcpy(&datetime[6], &date_str[4], 2); //date
if (datetime[6] == ' ')
datetime[6] = '0';
memcpy(&datetime[ 8], &time_str[0], 2); //hour
memcpy(&datetime[10], &time_str[3], 2); //min
memcpy(&datetime[12], &time_str[6], 2); //sec
}
#endif // #ifdef CONSOLE_DEBUG
/*******************(C)COPYRIGHT 2024 Amogreentech *********END OF FILE********/

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/*
*********************************************************************************************************
* EXAMPLE CODE
*
* (c) Copyright 2003-2007; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
* Knowledge of the source code may NOT be used to develop a similar product.
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* APPLICATION CONFIGURATION
*
* ST Microelectronics STM32
* with the
* IAR STM32-SK Evaluation Board
*
* Filename : app_cfg.h
* Version : V1.00
* Programmer(s) : FT
*********************************************************************************************************
*/
#ifndef __APP_VER_H__
#define __APP_VER_H__
#include <stm32f10x.h>
#define BD_MODEL "BMU-21S\0"
void GetAppVersion(u8 *ver);
void APPVerDisplay(void);
void GET_BUILD_DATETIME(u8 *datetime);
u16 GetAppVersionStr(u8 *vStr);
#endif

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/*****************************************************************************
*
* MSO Corporation
*
* File : asutil.c
* Compiler : IAR C 5.10C Kickstart
* Revision : $Revision: 1.0 $
* Date : $Date: 2010 / 07 / 16
* Updated by : $Author: Jongkwang Woo
*
* Support mail : spirit0305@naver.com
*
* Target platform : STM32F4 Cortex-M4 support
*
* AppNote : BPCB Application
*
* Description : Utility routines
*
****************************************************************************/
#define _ASUTIL_
#include "includes.h"
#include "asutil.h"
#include "console.h"
#include "usart.h"
#include "app_ver.h"
#include "delay.h"
#include "brtc.h"
u16 reverse16(u16 data)
{
return ((data >> 8) & 0x00FF) + ((data << 8) & 0xFF00);
}
u32 reverse32(u32 data)
{
return ((data >> 24) & 0x000000FF) +
((data >> 8) & 0x0000FF00) +
((data << 8) & 0x00FF0000) +
((data << 24) & 0xFF000000);
}
#ifndef CONSOLE_DEBUG
//void UART_DATA_PRINT(u16 port, u8 * buf, u16 len, u8 mode)
//{
//}
//void CAN_DATA_PRINT(u16 port, CanRxMsg* buf, u8 mode)
//{
//}
//void CAN_TX_DATA_PRINT(u16 port, CanTxMsg* buf)
//{
//}
void UserMessage(char *str)
{
}
#endif // #ifndef CONSOLE_DEBUG
#ifdef CONSOLE_DEBUG
u8 *dump_addr = 0;
void ClearConsol(void)
{
printf("%1c[ ; H [32;40m", 0x1b);
printf("%1c[2J%1c[0;0H%1c[2;37;40m", 0x1b, 0x1b, 0x1b);
}
void UserMessage(char *str)
{
char DisplayStr[81];
s16 i;
printf("%1c[s", 0x1b);
printf("%1c[24;01H%1c[34;47m", 0x1b, 0x1b);
for (i = 0; i < 80; i++)
{
DisplayStr[i] = ' ';
}
i = 0;
while ((str[i] != '\0') && (i < 80))
{
DisplayStr[i] = str[i];
i ++;
}
DisplayStr[80] = 0x00;
printf("%s", DisplayStr);
printf("%1c[37;40m%1c[23;8H", 0x1b, 0x1b);
printf("%1c[u", 0x1b);
}
void NormalOutXY(u16 x, u16 y, u8 *msg)
{
printf("%1c[s%1c[%02d;%02dH%1c[1m", 0x1b, 0x1b, y, x, 0x1b);
printf("%s", msg);
printf("%1c[23;8H%1c[u", 0x1b, 0x1b);
}
void GreenOutXY(u16 x,u16 y, u8 *msg)
{
printf("%1c[s%1c[%02d;%02dH%1c[1;32;40m", 0x1b, 0x1b, y, x, 0x1b);
printf("%s", msg);
printf("%1c[37;40m%1c[23;8H%1c[u", 0x1b, 0x1b, 0x1b);
}
void RedOutXY(u16 x,u16 y, u8 *msg)
{
printf("%1c[s%1c[%02d;%02dH%1c[1;31;40m", 0x1b, 0x1b, y, x, 0x1b);
printf("%s", msg);
printf("%1c[37;40m%1c[23;8H%1c[u", 0x1b, 0x1b, 0x1b);
}
void YellowOutXY(u16 x,u16 y, u8 *msg)
{
printf("%1c[s%1c[%02d;%02dH%1c[1;33;40m", 0x1b, 0x1b, y, x, 0x1b);
printf("%s", msg);
printf("%1c[37;40m%1c[23;8H%1c[u", 0x1b, 0x1b, 0x1b);
}
void ColorOutXY(u8 aColor, u16 x, u16 y, u8 *Text)
{
switch (aColor)
{
case DISPLAY_NORMAL:
NormalOutXY(x, y, Text);
break;
case DISPLAY_RED:
RedOutXY(x, y, Text);
break;
case DISPLAY_GREEN:
GreenOutXY(x, y, Text);
break;
case DISPLAY_YELLOW:
YellowOutXY(x, y, Text);
break;
}
}
void dump_mem(u32 addr)
{
u8 ASC[20];
s16 a,b;
if (addr != 0)
{
dump_addr = (u8 *)(addr);
}
printf("\r\n");
for (a = 0; a < 8; a++)
{
printf("%08lX ", (unsigned long)(dump_addr));
for (b = 0; b < 16; b++)
{
printf("%02X ", dump_addr[0]);
if (dump_addr[0] <' ') ASC[b] = '.';
else if (dump_addr[0] == 0xFF) ASC[b] = '.';
else
{
if ((b == 15)&&(dump_addr[0] > 128))
ASC[b] = '.';
else
ASC[b] = dump_addr[0];
}
dump_addr++;
}
printf(" ");
ASC[16] = 0x00;
printf("%s", ASC);
printf("\r\n");
}
}
u32 TextToAddr(u8 *data)
{
u32 l;
int a, b, c;
a = 0;
while (((data[a] >= '0') && (data[a] <= '9')) ||
((data[a] >= 'A') && (data[a] <= 'F')) ||
((data[a] >= 'a') && (data[a] <= 'f'))
)
{
a++;
}
l = 0;
for (b = 0; b < a; b++)
{
if (data[b] > 'F') { c = data[b] - 'a' + 10; }
else
{
if (data[b] > '9') { c = data[b] - 'A' + 10;}
else { c = data[b] - '0';}
}
l = l * 16 + c;
}
return(l);
}
u8 WaitUserCMD(u8 *cmd)
{
u32 waittime;
u8 ret;
u8 one[2];
u16 i, len;
for (i = 0; i < 20; i++)
{
if (cmd[i] == '\0') break;
}
len = i;
waittime = GetLocalTime() + 5;
ret = 0;
while (waittime > GetLocalTime())
{
if (debug_recv_data(one))
{
for (i = 0; i < len; i++)
{
if (one[0] == cmd[i])
return (i + 1);
}
}
IWDG_ReloadCounter();
delay_os_ms(1);
}
position = 0;
return(ret);
}
void data_print(u8 *data, u16 len)
{
u8 ASC[20];
u16 i, j;
for (i = 0; i < (len/16 + 1); i++)
{
printf("0x%04X ", (u32)(data + (i*16)));
for (j = 0; j < 16; j++)
{
if ((i*16 + j) >= len)
{
printf(" ");
ASC[j] = ' ';
}
else
{
printf("%02X ", data[(i*16)+j]);
if (data[i*16 + j] <' ') ASC[j] = '.';
else
{
if ((j == 15)&&(data[i*16 + j] > 128))
ASC[j] = '.';
else
ASC[j] = data[i*16 + j];
}
}
}
ASC[16] = 0x00;
printf(" %s\r\n", ASC);
}
}
void CAN_RX_DATA_PRINT(u16 port, CanRxMsg* buf)
{
printf("\r\nCAN%d RX: ID(0x%08X): DLC(%d): ", port, buf->ExtId, buf->DLC);
data_print(buf->Data, buf->DLC);
}
void CAN_TX_DATA_PRINT(u16 port, CanTxMsg* buf)
{
printf("\r\nCAN%d TX: ID(0x%08X): DLC(%d): ", port, buf->ExtId, buf->DLC);
data_print(buf->Data, buf->DLC);
}
void DebugMessage(u8 *msg)
{
if (screenmode == DIAG_MODE)
printf("%s", msg);
}
u8 FIND_CHAR(u8 *in, u8 *out, s16 max, u8 fdata)
{
u8 i;
if (max <= 0)
return 0;
for (i = 0; i < max; i++)
{
if (in[i] == fdata) break; // not found
out[i] = in[i];
}
return(i);
}
u8 FIND_DATA(u8 *in, u8 *out, u16 max, u8 fdata, u16 count)
{
u16 i, j, k, ret;
i = 0;
j = 0;
k = 0;
ret = 0;
for (i = 0; i < max; i++)
{
if (in[i] == 0x00) break;
if (in[i] == 0x03) break;
if (in[i] == fdata)
{
j++;
if (j == count)
{
ret = k;
break;
}
k = 0;
}
else
{
out[k++] = in[i];
}
}
return ret;
}
void FloatToStr(float ins, u8 *text, u16 size, u16 point)
{
u32 a = 1;
s32 b, x;
u32 y, k, i;
if (ins < 0) k = true; else k = false;
if (point > 0)
{
for (i = 0; i < point; i++)
a *= 10;
b = (s32)(ins * a);
if (b < 0) b *= -1;
x = (s32)ins;
y = (u32)(b % a);
}
else
{
x = (s32)ins;
y = 0;
}
text[0] = 0x00;
switch (size)
{
case 0:
break;
case 1:
sprintf((char *)text, "%1d", x);
break;
case 2:
sprintf((char *)text, "%2d", x);
break;
case 3:
switch (point)
{
case 0:
sprintf((char *)text, "%3d", x);
break;
case 1:
sprintf((char *)text, "%1d.%01d", x, y);
break;
}
break;
case 4:
switch (point)
{
case 0:
sprintf((char *)text, "%4d", x);
break;
case 1:
sprintf((char *)text, "%2d.%01d", x, y);
break;
case 2:
sprintf((char *)text, "%1d.%02d", x, y);
break;
}
break;
case 5:
switch (point)
{
case 0:
sprintf((char *)text, "%5d", x);
break;
case 1:
sprintf((char *)text, "%3d.%01d", x, y);
break;
case 2:
sprintf((char *)text, "%2d.%02d", x, y);
break;
case 3:
sprintf((char *)text, "%1d.%03d", x, y);
break;
}
break;
case 6:
switch (point)
{
case 0:
sprintf((char *)text, "%6d", x);
break;
case 1:
sprintf((char *)text, "%4d.%01d", x, y);
break;
case 2:
sprintf((char *)text, "%3d.%02d", x, y);
break;
case 3:
sprintf((char *)text, "%2d.%03d", x, y);
break;
case 4:
sprintf((char *)text, "%1d.%04d", x, y);
break;
}
break;
case 7:
switch (point)
{
case 0:
sprintf((char *)text, "%7d", x);
break;
case 1:
sprintf((char *)text, "%5d.%01d", x, y);
break;
case 2:
sprintf((char *)text, "%4d.%02d", x, y);
break;
case 3:
sprintf((char *)text, "%3d.%03d", x, y);
break;
case 4:
sprintf((char *)text, "%2d.%04d", x, y);
break;
case 5:
sprintf((char *)text, "%1d.%05d", x, y);
break;
}
break;
case 8:
switch (point)
{
case 0:
sprintf((char *)text, "%7d", x);
break;
case 1:
sprintf((char *)text, "%5d.%01d", x, y);
break;
case 2:
sprintf((char *)text, "%4d.%02d", x, y);
break;
case 3:
sprintf((char *)text, "%3d.%03d", x, y);
break;
case 4:
sprintf((char *)text, "%2d.%04d", x, y);
break;
case 5:
sprintf((char *)text, "%1d.%05d", x, y);
break;
case 6:
sprintf((char *)text, "%1d.%06d", x, y);
break;
}
break;
}
if ((x == 0)&&(k == true)) text[0] = '-';
}
void FloatColorOutIntXY(u8 Color, u16 x,u16 y, float Value, u16 Length, u16 Point)
{
u8 temp[10];
FloatToStr(Value, temp, Length, Point);
temp[Length] = 0x00;
ColorOutXY(Color, x, y, temp);
}
/* ¼Ò¼öÁ¡ = Point */
void FloatNormalOutIntXY(u16 x,u16 y, float Value, u16 Length, u16 Point)
{
u8 temp[10];
FloatToStr(Value, temp, Length, Point);
temp[Length] = 0x00;
GreenOutXY(x,y,temp);
}
void FloatRedOutIntXY(u16 x,u16 y, float Value, s16 Length, u16 Point)
{
u8 temp[10];
FloatToStr(Value, temp, Length, Point);
temp[Length] = 0x00;
RedOutXY(x, y, temp);
}
char digit2ascii(u8 t)
{
char k;
if (t < 10 ) k = '0' + (char)t;
else if( t == 10) k = 'A';
else if( t == 11) k = 'B';
else if( t == 12) k = 'C';
else if( t == 13) k = 'D';
else if( t == 14) k = 'E';
else if( t == 15) k = 'F';
return(k);
}
s16 ascii2digit(u8 t)
{
s16 k;
k = 0;
switch (t)
{
case '0' : k = 0; break;
case '1' : k = 1; break;
case '2' : k = 2; break;
case '3' : k = 3; break;
case '4' : k = 4; break;
case '5' : k = 5; break;
case '6' : k = 6; break;
case '7' : k = 7; break;
case '8' : k = 8; break;
case '9' : k = 9; break;
case 'a' :
case 'A' : k =10; break;
case 'b' :
case 'B' : k =11; break;
case 'c' :
case 'C' : k =12; break;
case 'd' :
case 'D' : k =13; break;
case 'e' :
case 'E' : k =14; break;
case 'f' :
case 'F' : k =15; break;
}
return(k);
}
void IntToStr(s16 ins, u8 *text, s16 size)
{
s16 i, one, two, a;
a = 1;
if (ins < 0)
{
one = -1* ins;
a = -1;
}
else
{
one = ins;
}
for(i = (size - 1); i >= 0; i--)
{
two = one / 10;
text[i] = one % 10 + '0';
one = two;
}
if (a < 0)
{
text[0] = '-';
}
}
void Int32ToStr(u32 ins, u8 *text, u16 size)
{
s16 i;
u32 one, two;
one = ins;
for(i = (size - 1); i >= 0; i--)
{
two = one / 10;
text[i] = one % 10 + '0';
one = two;
}
}
s16 StrToInt(u8 *text, u16 size)
{
s16 a = 1, i, k = 0;
for (i = (size -1); i >= 0; i--)
{
if (text[i] != '-')
{
k += (text[i] - '0') * a;
a *= 10;
}
else
{
k = -1 * k;
}
}
return(k);
}
u8 Str2ToHex(u8 *text, u16 size)
{
s16 a = 1, i, k = 0;
for (i = (size -1); i >= 0; i--)
{
if ((text[i] >= '0')&&(text[i] <= '9'))
{
k += (text[i] - '0') * a;
a *= 16;
}
else if ((text[i] >= 'A')&&(text[i] <= 'F'))
{
k += (text[i] - 'A' + 10) *a;
a *= 16;
}
else if ((text[i] >= 'a')&&(text[i] <= 'f'))
{
k += (text[i] - 'a' + 10) *a;
a *= 16;
}
}
return(k);
}
u32 strtohex(char *string, int size)
{
int i, sh;
u32 result = 0;
char *ptr = string;
for (i = 0; i < size; i++)
{
sh = (size - i - 1) * 4;
result += ascii2digit(ptr[i]) << sh;
}
return result;
}
u32 StrToInt32(u8 *text, u16 size)
{
s16 i;
u32 a = 1, k = 0;
for (i = (size -1); i >= 0; i--)
{
// if ((text[i] >= '0')&&(text[i] < '9'))
// {
k += (text[i] - '0') * a;
a *= 10;
// }
}
return(k);
}
void Int2Hex(u8 c, u8 *temp)
{
s16 a,b;
a = c / 16;
b = c % 16;
if (a > 9) {temp[0] = a + 'A' - 10;}
else{temp[0] = a + '0';}
if (b > 9) {temp[1] = b + 'A' - 10;}
else{temp[1] = b + '0';}
}
void IntOneHex(u8 c, u8 *temp)
{
if (c > 9) {temp[0] = c + 'A' - 10;}
else{temp[0] = c + '0';}
}
void LongToStr(u16 a, u16 b, u8 *temp)
{
u16 t;
u16 j;
for (j = 8 - b; j < 8; j++)
{
t = (a >> (28 - (4 * j))) & 0x0f;
temp[j] = digit2ascii(t);
}
temp[8] = ' ';
temp[9] = 0x00;
}
u8 str2bcd(u8 *a)
{
u8 i, j;
j = 0;
for (i = 0; i < 2; i++) {
if ((a[i] <= '9') && (a[i] >= '0')) j = j + (a[i] - '0');
if ((a[i] <= 'F') && (a[i] >= 'A')) j = j + (a[i] - 'A') + 10;
if ((a[i] <= 'f') && (a[i] >= 'a')) j = j + (a[i] - 'a') + 10;
if (i == 0) j <<= 4;
}
return j;
}
void bcdstr2(u8 in, u8 *out)
{
u8 i, j;
i = (in >> 4)& 0xF;
j = (in)& 0xF;
out[0] = i + '0';
out[1] = j + '0';
}
void StrToBCD(u8 *in, u8 *out, u16 size)
{
u16 i;
for (i = 0; i < size; i++)
{
out[i] = str2bcd(&in[i * 2]);
}
}
u8 Make_BCC(u8 *data, u16 len)
{
u16 i;
u8 bcc = 0;
for (i = 0; i < (len - 2); i++)
{
bcc ^= data[1 + i];
}
return bcc;
}
u8 MakeCheckSum(u8 *data, u8 size)
{
u8 i, sum;
sum = 0;
for (i = 4; i < (size - 2); i++)
{
sum += data[i];
}
return sum;
}
u16 StrToF2P(u8 *text, u16 size)
{
u16 i, j;
u8 temp[20];
u16 aParam[2];
u16 result;
i = 0;
j = FIND_CHAR((u8 *)&text[i], temp, size - i, '.');
i = i + j + 1;
aParam[0] = StrToInt(temp, j);
temp[j] = 0x00;
j = FIND_CHAR((u8 *)&text[i], temp, size - i, '.');
i = i + j + 1;
aParam[1] = StrToInt(temp, j);
temp[j] = 0x00;
switch (j)
{
case 0:
result = aParam[0] * 100;
break;
case 1:
result = ((aParam[0] * 10) + aParam[1]) * 10;
break;
case 2:
result = (aParam[0] * 100) + aParam[1];
break;
case 3:
result = ((aParam[0] * 1000) + aParam[1]) / 10;
break;
}
return result;
}
#endif // #ifdef CONSOLE_DEBUG
/****************** End of Asutil.c *********************/

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/*****************************************************************************
*
* MSO Corporation
*
* File : asutil.h
* Compiler : IAR C 5.30C Kickstart
* Revision : $Revision: 1.0 $
* Date : $Date: 2010 / 7 / 16
* Updated by : $Author: Jongkwang Woo
*
* Support mail : spirit0305@naver.com
*
* Target platform : STM32F4 Cortex-M4 support
*
* AppNote : BPCB Application
*
* Description : Header file for asutil.c
*
****************************************************************************/
#ifndef _ASUTIL_H_
#define _ASUTIL_H_
#include <stm32f10x.h>
#pragma pack(1)
#define RX_PRINT 0
#define TX_PRINT 1
#define TCP_RX_PRINT 2
#define TCP_TX_PRINT 3
#define ACT 1
#define WAIT 0
#define High 1
#define Low 0
#define ON 1
#define OFF 0
#define SET 1
#define CLEAR 0
#define DISPLAY_NORMAL 0x00
#define DISPLAY_RED 0x01
#define DISPLAY_GREEN 0x02
#define DISPLAY_YELLOW 0x03
extern u8 *dump_addr;
/* find charater funcion ************************************************/
u8 FIND_CHAR(u8 *in, u8 *out, s16 max, u8 fdata);
u8 FIND_DATA(u8 *in, u8 *out, u16 max, u8 fdata, u16 count);
/************************************************************************/
char digit2ascii(u8 t);
s16 ascii2digit(u8 t);
u8 WaitUserCMD(u8 *cmd);
void UserMessage(char *str);
void ColorOutXY(u8 aColor, u16 x, u16 y, u8 *Text);
void RedOutXY(u16 x,u16 y, u8 *msg);
void GreenOutXY(u16 x,u16 y, u8 *msg);
void YellowOutXY(u16 x,u16 y, u8 *msg);
void NormalOutXY(u16 x,u16 y, u8 *msg);
void OutXY(u8 aRED, u16 x, u16 y, u8 *Text);
void FloatNormalOutIntXY(u16 x,u16 y, float Value, u16 Length, u16 Point);
void FloatRedOutIntXY(u16 x,u16 y, float Value, s16 Length, u16 Point);
void FloatColorOutIntXY(u8 Color, u16 x,u16 y, float Value, u16 Length, u16 Point);
void ClearConsol (void);
void DebugMessage(u8 *msg);
s16 StrToInt(u8 *text, u16 size);
u32 StrToInt32(u8 *text, u16 size);
void IntToStr(s16 ins, u8 *text, s16 size);
void Int32ToStr(u32 ins, u8 *text, u16 size);
void IntToHex(u16 ins, u8 *text, u8 size);
void Int2Hex(u8 c, u8 *temp);
void LongToStr(u16 a, u16 b, u8 *temp);
u8 Str2ToHex(u8 *text, u16 size);
void IntOneHex(u8 c, u8 *temp);
void Int32ToStrD(s32 ins, u8 *text, u16 size);
void FloatToStr(float ins, u8 *text, u16 size, u16 point);
u32 TextToAddr(u8 *data);
void dump_mem(u32 addr);
u8 str2bcd(u8 *a);
void StrToBCD(u8 *in, u8 *out, u16 size);
void StrToBCD2(u8 *in, u8 *out, u16 isize, u16 osize);
void Int32ToBCD(u32 in32, u8 *out, u16 osize);
void BCDToStr(u8 *in, u8 *out, u16 size);
u32 BCDToInt32(u8 *in, u16 size);
void data_print(u8 *data, u16 len);
void CAN_RX_DATA_PRINT(u16 port, CanRxMsg* buf);
void CAN_TX_DATA_PRINT(u16 port, CanTxMsg* buf);
void RTC_MEM_Dump(u16 page);
u8 Make_BCC(u8 *data, u16 len);
u8 MakeCheckSum(u8 *data, u8 size);
u16 reverse16(u16 data);
u32 reverse32(u32 data);
u32 strtohex(char *string, int size);
#pragma pack()
#endif

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#ifndef bms_master_H
#define bms_master_H
#include "sys.h"
#define IC_LTC6813
#define MD_422HZ_1KHZ 0
#define MD_27KHZ_14KHZ 1
#define MD_7KHZ_3KHZ 2
#define MD_26HZ_2KHZ 3
#define ADC_OPT_ENABLED 1
#define ADC_OPT_DISABLED 0
#define CELL_CH_ALL 0
#define CELL_CH_1and7 1
#define CELL_CH_2and8 2
#define CELL_CH_3and9 3
#define CELL_CH_4and10 4
#define CELL_CH_5and11 5
#define CELL_CH_6and12 6
#define SELFTEST_1 1
#define SELFTEST_2 2
#define AUX_CH_ALL 0
#define AUX_CH_GPIO1 1
#define AUX_CH_GPIO2 2
#define AUX_CH_GPIO3 3
#define AUX_CH_GPIO4 4
#define AUX_CH_GPIO5 5
#define AUX_CH_VREF2 6
#define STAT_CH_ALL 0
#define STAT_CH_SOC 1
#define STAT_CH_ITEMP 2
#define STAT_CH_VREGA 3
#define STAT_CH_VREGD 4
#define DCP_DISABLED 0
#define DCP_ENABLED 1
#define PULL_UP_CURRENT 1
#define PULL_DOWN_CURRENT 0
#define NUM_RX_BYT 8
#define CELL 1
#define AUX 2
#define STAT 3
#define CFGR 0
#define CFGRB 4
#define CS_PIN PBout(12) //The chip select signals
//! Cell Voltage data structure.
typedef struct
{
uint16_t c_codes[18]; //!< Cell Voltage Codes
uint8_t pec_match[6]; //!< If a PEC error was detected during most recent read cmd
} cv;
//! AUX Reg Voltage Data
typedef struct
{
uint16_t a_codes[9]; //!< Aux Voltage Codes
uint8_t pec_match[4]; //!< If a PEC error was detected during most recent read cmd
} ax;
typedef struct
{
uint16_t stat_codes[4]; //!< A two dimensional array of the stat voltage codes.
uint8_t flags[3]; //!< byte array that contains the uv/ov flag data
uint8_t mux_fail[1]; //!< Mux self test status flag
uint8_t thsd[1]; //!< Thermal shutdown status
uint8_t pec_match[2]; //!< If a PEC error was detected during most recent read cmd
} st;
typedef struct
{
uint8_t tx_data[6];
uint8_t rx_data[8];
uint8_t rx_pec_match; //!< If a PEC error was detected during most recent read cmd
} ic_register;
typedef struct
{
uint16_t pec_count;
uint16_t cfgr_pec;
uint16_t cell_pec[6];
uint16_t aux_pec[4];
uint16_t stat_pec[2];
} pec_counter;
typedef struct
{
uint8_t cell_channels;
uint8_t stat_channels;
uint8_t aux_channels;
uint8_t num_cv_reg;
uint8_t num_gpio_reg;
uint8_t num_stat_reg;
} register_cfg;
typedef uint8_t bool;
typedef struct
{
ic_register config;
ic_register configb;
cv cells;
ax aux;
st stat;
ic_register com;
ic_register pwm;
ic_register pwmb;
ic_register sctrl;
ic_register sctrlb;
bool isospi_reverse;
pec_counter crc_count;
register_cfg ic_reg;
long system_open_wire;
} cell_asic;
/*! calculates and returns the CRC15
@returns The calculated pec15 as an unsigned int
*/
uint16_t pec15_calc(uint8_t len, //!< the length of the data array being passed to the function
uint8_t *data //!< the array of data that the PEC will be generated from
);
/*! Wake isoSPI up from idle state */
void wakeup_idle(uint8_t total_ic);//!< number of ICs in the daisy chain
/*! Wake the LTC6813 from the sleep state */
void wakeup_sleep(uint8_t total_ic); //!< number of ICs in the daisy chain
/*! Sense a command to the bms IC. This code will calculate the PEC code for the transmitted command*/
void cmd_68(uint8_t tx_cmd[2]); //!< 2 Byte array containing the BMS command to be sent
//! Writes an array of data to the daisy chain
void write_68(uint8_t total_ic , //!< number of ICs in the daisy chain
uint8_t tx_cmd[2], //!< 2 Byte array containing the BMS command to be sent
uint8_t data[] //!< Array containing the data to be written to the BMS ICs
);
//! Issues a command onto the daisy chain and reads back 6*total_ic data in the rx_data array
int8_t read_68( uint8_t total_ic, //!< number of ICs in the daisy chain
uint8_t tx_cmd[2], //!< 2 Byte array containing the BMS command to be sent
uint8_t *rx_data); //!< Array that the read back data will be stored.
/*! Starts the Mux Decoder diagnostic self test
Running this command will start the Mux Decoder Diagnostic Self Test
This test takes roughly 1mS to complete. The MUXFAIL bit will be updated,
the bit will be set to 1 for a failure and 0 if the test has been passed.
*/
void LTC681x_diagn(void);
//! Sends the poll adc command
//! @returns 1 byte read back after a pladc command. If the byte is not 0xFF ADC conversion has completed
uint8_t LTC681x_pladc(void);
//! This function will block operation until the ADC has finished it's conversion
//! @returns the approximate time it took for the ADC function to complete.
uint32_t LTC681x_pollAdc(void);
/*! Starts cell voltage conversion
Starts ADC conversions of the LTC6811 Cpin inputs.
The type of ADC conversion executed can be changed by setting the following parameters:
*/
void LTC681x_adcv(uint8_t MD, //!< ADC Conversion Mode
uint8_t DCP, //!< Controls if Discharge is permitted during conversion
uint8_t CH //!< Sets which Cell channels are converted
);
/*! Starts cell voltage and GPIO 1&2 conversion
*/
void LTC681x_adcvax(
uint8_t MD, //!< ADC Conversion Mode
uint8_t DCP //!< Controls if Discharge is permitted during conversion
);
/*! Starts cell voltage self test conversion
*/
void LTC681x_cvst(
uint8_t MD, //!< ADC Conversion Mode
uint8_t ST //!< Self Test Mode
);
/*! Starts cell voltage and SOC conversion
*/
void LTC681x_adcvsc(
uint8_t MD, //!< ADC Conversion Mode
uint8_t DCP //!< Controls if Discharge is permitted during conversion
);
/*! Starts cell voltage overlap conversion
*/
void LTC681x_adol(
uint8_t MD, //!< ADC Conversion Mode
uint8_t DCP //!< Discharge permitted during conversion
);
/*! Start an open wire Conversion
*/
void LTC681x_adow(
uint8_t MD, //!< ADC Conversion Mode
uint8_t PUP //!< Controls if Discharge is permitted during conversion
);
/*! Start a GPIO and Vref2 Conversion
*/
void LTC681x_adax(
uint8_t MD, //!< ADC Conversion Mode
uint8_t CHG //!< Sets which GPIO channels are converted
);
/*! Start an GPIO Redundancy test
*/
void LTC681x_adaxd(
uint8_t MD, //!< ADC Conversion Mode
uint8_t CHG //!< Sets which GPIO channels are converted
);
/*! Start an Auxiliary Register Self Test Conversion
*/
void LTC681x_axst(
uint8_t MD, //!< ADC Conversion Mode
uint8_t ST //!< Sets if self test 1 or 2 is run
);
/*! Start a Status ADC Conversion
*/
void LTC681x_adstat(
uint8_t MD, //!< ADC Conversion Mode
uint8_t CHST //!< Sets which Stat channels are converted
);
/*! Start a Status register redundancy test Conversion
*/
void LTC681x_adstatd(
uint8_t MD, //!< ADC Mode
uint8_t CHST //!< Sets which Status channels are converted
);
/*! Start a Status Register Self Test Conversion
*/
void LTC681x_statst(
uint8_t MD, //!< ADC Conversion Mode
uint8_t ST //!< Sets if self test 1 or 2 is run
);
void LTC681x_rdcv_reg(uint8_t reg, //!<Determines which cell voltage register is read back
uint8_t total_ic, //!<the number of ICs in the
uint8_t *data //!<An array of the unparsed cell codes
);
/*! helper function that parses voltage measurement registers
*/
int8_t parse_cells(uint8_t current_ic,
uint8_t cell_reg,
uint8_t cell_data[],
uint16_t *cell_codes,
uint8_t *ic_pec);
/*! Read the raw data from the LTC681x auxiliary register
The function reads a single GPIO voltage register and stores thre read data
in the *data point as a byte array. This function is rarely used outside of
the LTC681x_rdaux(void) command.
*/
void LTC681x_rdaux_reg( uint8_t reg, //Determines which GPIO voltage register is read back
uint8_t total_ic, //The number of ICs in the system
uint8_t *data //Array of the unparsed auxiliary codes
);
/*! Read the raw data from the LTC681x stat register
The function reads a single GPIO voltage register and stores thre read data
in the *data point as a byte array. This function is rarely used outside of
the LTC681x_rdstat(void) command.
*/
void LTC681x_rdstat_reg(uint8_t reg, //Determines which stat register is read back
uint8_t total_ic, //The number of ICs in the system
uint8_t *data //Array of the unparsed stat codes
);
/*! Clears the LTC681x cell voltage registers
The command clears the cell voltage registers and initializes
all values to 1. The register will read back hexadecimal 0xFF
after the command is sent.
*/
void LTC681x_clrcell(void);
/*! Clears the LTC681x Auxiliary registers
The command clears the Auxiliary registers and initializes
all values to 1. The register will read back hexadecimal 0xFF
after the command is sent.
*/
void LTC681x_clraux(void);
/*! Clears the LTC681x Stat registers
The command clears the Stat registers and initializes
all values to 1. The register will read back hexadecimal 0xFF
after the command is sent.
*/
void LTC681x_clrstat(void);
/*! Clears the LTC681x SCTRL registers
The command clears the SCTRL registers and initializes
all values to 0. The register will read back hexadecimal 0x00
after the command is sent.
*/
void LTC681x_clrsctrl(void);
/*! Starts the Mux Decoder diagnostic self test
Running this command will start the Mux Decoder Diagnostic Self Test
This test takes roughly 1mS to complete. The MUXFAIL bit will be updated,
the bit will be set to 1 for a failure and 0 if the test has been passed.
*/
void LTC681x_diagn(void);
/*! Reads and parses the LTC681x cell voltage registers.
The function is used to read the cell codes of the LTC6811.
This function will send the requested read commands parse the data
and store the cell voltages in the cell_asic structure.
*/
uint8_t LTC681x_rdcv(uint8_t reg, // Controls which cell voltage register is read back.
uint8_t total_ic, // the number of ICs in the system
cell_asic ic[] // Array of the parsed cell codes
);
/*! Reads and parses the LTC681x auxiliary registers.
The function is used to read the parsed GPIO codes of the LTC6811. This function will send the requested
read commands parse the data and store the gpio voltages in the cell_asic structure.
*/
int8_t LTC681x_rdaux(uint8_t reg, //Determines which GPIO voltage register is read back.
uint8_t total_ic,//the number of ICs in the system
cell_asic ic[]//!< Measurement Data Structure
);
/*! Reads and parses the LTC681x stat registers.
The function is used to read the parsed status codes of the LTC6811. This function will send the requested
read commands parse the data and store the status voltages in the cell_asic structure
*/
int8_t LTC681x_rdstat( uint8_t reg, //!<Determines which Stat register is read back.
uint8_t total_ic,//!<the number of ICs in the system
cell_asic ic[]//!< Measurement Data Structure
);
/*! Write the LTC681x CFGRA
This command will write the configuration registers of the LTC681xs
connected in a daisy chain stack. The configuration is written in descending
order so the last device's configuration is written first.
*/
void LTC681x_wrcfg(uint8_t total_ic, //The number of ICs being written to
cell_asic ic[] //A two dimensional array of the configuration data that will be written
);
/*! Reads the LTC681x CFGRA register
*/
int8_t LTC681x_rdcfg(uint8_t total_ic, //Number of ICs in the system
cell_asic ic[] //A two dimensional array that the function stores the read configuration data.
);
/*! Selft Test Helper Function*/
uint16_t LTC681x_st_lookup(
uint8_t MD, //ADC Mode
uint8_t ST //Self Test
);
/*! Helper Function to clear DCC bits in the CFGR Registers*/
void clear_discharge(uint8_t total_ic,
cell_asic ic[]);
/*! Helper function that runs the ADC Self Tests*/
int16_t LTC681x_run_cell_adc_st(uint8_t adc_reg,
uint8_t total_ic,
cell_asic ic[]);
/*! Helper function that runs the ADC Digital Redudancy commands and checks output for errors*/
int16_t LTC681x_run_adc_redundancy_st(uint8_t adc_mode,
uint8_t adc_reg,
uint8_t total_ic,
cell_asic ic[]);
/*! Helper function that runs the datasheet open wire algorithm*/
void LTC681x_run_openwire(uint8_t total_ic,
cell_asic ic[]);
/*! Helper Function that runs the ADC Overlap test*/
uint16_t LTC681x_run_adc_overlap(uint8_t total_ic,
cell_asic ic[]);
/*! Helper Function that counts overall PEC errors and register/IC PEC errors*/
void LTC681x_check_pec(uint8_t total_ic,
uint8_t reg,
cell_asic ic[]);
/*! Helper Function that resets the PEC error counters */
void LTC681x_reset_crc_count(uint8_t total_ic,
cell_asic ic[]);
/*! Helper Function to initialize the CFGR data structures*/
void LTC681x_init_cfg(uint8_t total_ic,
cell_asic ic[]);
/*! Helper function to set appropriate bits in CFGR register based on bit function*/
void LTC681x_set_cfgr(uint8_t nIC,
cell_asic ic[],
bool refon,
bool adcopt,
bool gpio[5],
bool dcc[12]);
/*! Helper function to turn the refon bit HIGH or LOW*/
void LTC681x_set_cfgr_refon(uint8_t nIC,
cell_asic ic[],
bool refon);
/*! Helper function to turn the ADCOPT bit HIGH or LOW*/
void LTC681x_set_cfgr_adcopt(uint8_t nIC,
cell_asic ic[],
bool adcopt);
/*! Helper function to turn the GPIO bits HIGH or LOW*/
void LTC681x_set_cfgr_gpio(uint8_t nIC,
cell_asic ic[],
bool gpio[]);
/*! Helper function to turn the DCC bits HIGH or LOW*/
void LTC681x_set_cfgr_dis(uint8_t nIC,
cell_asic ic[],
bool dcc[]);
////This needs a PROGMEM = when using with a LINDUINO
//const uint16_t crc15Table[256] = {
// 0x0000, 0xc599, 0xceab, 0x0b32, 0xd8cf, 0x1d56, 0x1664, 0xd3fd, 0xf407, 0x319e, 0x3aac, //!<precomputed CRC15 Table
// 0xff35, 0x2cc8, 0xe951, 0xe263, 0x27fa, 0xad97, 0x680e, 0x633c, 0xa6a5, 0x7558, 0xb0c1,
// 0xbbf3, 0x7e6a, 0x5990, 0x9c09, 0x973b, 0x52a2, 0x815f, 0x44c6, 0x4ff4, 0x8a6d, 0x5b2e,
// 0x9eb7, 0x9585, 0x501c, 0x83e1, 0x4678, 0x4d4a, 0x88d3, 0xaf29, 0x6ab0, 0x6182, 0xa41b,
// 0x77e6, 0xb27f, 0xb94d, 0x7cd4, 0xf6b9, 0x3320, 0x3812, 0xfd8b, 0x2e76, 0xebef, 0xe0dd,
// 0x2544, 0x02be, 0xc727, 0xcc15, 0x098c, 0xda71, 0x1fe8, 0x14da, 0xd143, 0xf3c5, 0x365c,
// 0x3d6e, 0xf8f7, 0x2b0a, 0xee93, 0xe5a1, 0x2038, 0x07c2, 0xc25b, 0xc969, 0x0cf0, 0xdf0d,
// 0x1a94, 0x11a6, 0xd43f, 0x5e52, 0x9bcb, 0x90f9, 0x5560, 0x869d, 0x4304, 0x4836, 0x8daf,
// 0xaa55, 0x6fcc, 0x64fe, 0xa167, 0x729a, 0xb703, 0xbc31, 0x79a8, 0xa8eb, 0x6d72, 0x6640,
// 0xa3d9, 0x7024, 0xb5bd, 0xbe8f, 0x7b16, 0x5cec, 0x9975, 0x9247, 0x57de, 0x8423, 0x41ba,
// 0x4a88, 0x8f11, 0x057c, 0xc0e5, 0xcbd7, 0x0e4e, 0xddb3, 0x182a, 0x1318, 0xd681, 0xf17b,
// 0x34e2, 0x3fd0, 0xfa49, 0x29b4, 0xec2d, 0xe71f, 0x2286, 0xa213, 0x678a, 0x6cb8, 0xa921,
// 0x7adc, 0xbf45, 0xb477, 0x71ee, 0x5614, 0x938d, 0x98bf, 0x5d26, 0x8edb, 0x4b42, 0x4070,
// 0x85e9, 0x0f84, 0xca1d, 0xc12f, 0x04b6, 0xd74b, 0x12d2, 0x19e0, 0xdc79, 0xfb83, 0x3e1a, 0x3528,
// 0xf0b1, 0x234c, 0xe6d5, 0xede7, 0x287e, 0xf93d, 0x3ca4, 0x3796, 0xf20f, 0x21f2, 0xe46b, 0xef59,
// 0x2ac0, 0x0d3a, 0xc8a3, 0xc391, 0x0608, 0xd5f5, 0x106c, 0x1b5e, 0xdec7, 0x54aa, 0x9133, 0x9a01,
// 0x5f98, 0x8c65, 0x49fc, 0x42ce, 0x8757, 0xa0ad, 0x6534, 0x6e06, 0xab9f, 0x7862, 0xbdfb, 0xb6c9,
// 0x7350, 0x51d6, 0x944f, 0x9f7d, 0x5ae4, 0x8919, 0x4c80, 0x47b2, 0x822b, 0xa5d1, 0x6048, 0x6b7a,
// 0xaee3, 0x7d1e, 0xb887, 0xb3b5, 0x762c, 0xfc41, 0x39d8, 0x32ea, 0xf773, 0x248e, 0xe117, 0xea25,
// 0x2fbc, 0x0846, 0xcddf, 0xc6ed, 0x0374, 0xd089, 0x1510, 0x1e22, 0xdbbb, 0x0af8, 0xcf61, 0xc453,
// 0x01ca, 0xd237, 0x17ae, 0x1c9c, 0xd905, 0xfeff, 0x3b66, 0x3054, 0xf5cd, 0x2630, 0xe3a9, 0xe89b,
// 0x2d02, 0xa76f, 0x62f6, 0x69c4, 0xac5d, 0x7fa0, 0xba39, 0xb10b, 0x7492, 0x5368, 0x96f1, 0x9dc3,
// 0x585a, 0x8ba7, 0x4e3e, 0x450c, 0x8095
// };
//********************************** LTC6811 ******************************************//
void LTC6811_init_reg_limits(uint8_t total_ic, cell_asic ic[]);
void LTC6811_set_discharge(int Cell,
uint8_t total_ic,
cell_asic ic[]);
//********************************** SPI ******************************************//
/*
Writes an array of bytes out of the SPI port
*/
void spi_write_array(uint8_t len, // Option: Number of bytes to be written on the SPI port
uint8_t data[] //Array of bytes to be written on the SPI port
);
/*
Writes and read a set number of bytes using the SPI port.
*/
void spi_write_read(uint8_t tx_Data[],//array of data to be written on SPI port
uint8_t tx_len, //length of the tx data arry
uint8_t *rx_data,//Input: array that will store the data read by the SPI port
uint8_t rx_len //Option: number of bytes to be read from the SPI port
);
uint8_t spi_read_byte(uint8_t tx_dat);//name conflicts with linduino also needs to take a byte as a parameter
void App_TaskBatt(void);
#endif

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/**
******************************************************************************
* File Name : battery_comm.c
* Description : This file provides code for the configuration
* of CAN communication.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include <includes.h>
#include "delay.h"
#include "spi.h"
#include "battery_comm.h"
/* Private define ------------------------------------------------------------*/
#define BATT_TASK_TIME 1000 // 10ms TASK
#define COMMAND_PLADC 0x0714
#define COMMAND_ADCV 0x0360 //0x0360
#define COMMAND_RDCVA 0x8004
#define COMMAND_RDCVB 0x8006
#define COMMAND_RDCVC 0x8008
#define COMMAND_RDCVD 0x80A0
#define COMMAND_RDCFG 0x8002
#define BLOCK_SIZE 4
#define LTC6813_MAX_IC_COUNT 2
#define LTC6813_COMM_BUF_SIZE (4 + (8 * LTC6813_MAX_IC_COUNT)) // 20 bytes
static uint8_t g_ltc_comm_buffer[LTC6813_COMM_BUF_SIZE];
#define LTC6813_CS PBout(12) // The chip select signals LTC6813 (LTC6820)
void send_wakeup_signal(void);
/**
* Set up and initialize the interface with the battery bottle.
*/
void init_battery_interface(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); // GPIOB clock
//SPI_NSS - GPIOB12
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; // GPIO Line
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; // GPIO Speed
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; // GPIO In/Out
GPIO_Init(GPIOB, &GPIO_InitStructure);
LTC6813_CS = 1; // SPI FLASH is not selected
SPI2_Init(); // Initialize the SPI
SPI2_SetSpeed(SPI_BaudRatePrescaler_2); // Set to 42M clock high-speed mode
send_wakeup_signal();
}
/**
* @brief Initialize the Ethernet Module communication application
* @param None
* @retval None
*/
void App_TaskBatt(void)
{
init_battery_interface();
while (DEF_TRUE)
{
send_wakeup_signal();
delay_os_ms(BATT_TASK_TIME);
}
}
/**
* Obtains the voltage value for battery cells in Cell Group A.
*
* \param[out] cells a pointer to an array of size 6. Destination buffer for
* the battery cell voltage values.
*/
void request_battery_voltage_A(uint16_t *cells)
{
request_battery_voltage(COMMAND_RDCVA, 0x77D6, cells);
}
/**
* Obtains the voltage value for battery cells in Cell Group B.
*
* \param[out] cells a pointer to an array of size 6. Destination buffer for
* the battery cell voltage values.
*/
void request_battery_voltage_B(uint16_t *cells)
{
request_battery_voltage(COMMAND_RDCVB, 0xEA80, cells);
}
/**
* Obtains the voltage value for battery cells in Cell Group C.
*
* \param[out] cells a pointer to an array of size 6. Destination buffer for
* the battery cell voltage values.
*/
void request_battery_voltage_C(uint16_t *cells)
{
request_battery_voltage(COMMAND_RDCVC, 0x2E46, cells);
}
/**
* Obtains the voltage value for battery cells in Cell Group D.
*
* \param[out] cells a pointer to an array of size 6. Destination buffer for
* the battery cell voltage values.
*/
void request_battery_voltage_D(uint16_t *cells)
{
request_battery_voltage(COMMAND_RDCVD, 0xB310, cells);
}
/**
* Obtains the voltage value the battery cells from the specified group.
*
* \param[in] cell_group the SPI command code for the battery cell group
* COMMAND_RDCVA (Cell Group A)
* COMMAND_RDCVB (Cell Group B)
* COMMAND_RDCVC (Cell Group C)
* COMMAND_RDCVD (Cell Group D)
* \param[out] cells a pointer to an array of size 6. Destination buffer for
* the battery cell voltage values.
*/
void request_battery_voltage(uint16_t cell_group, uint16_t pec, uint16_t *cells)
{
uint16_t txBuf[] = {0x03, 0x60, 0xF4, 0x6C};// = {cell_group, pec};
//uint16_t txBuf[] = {0x6C, 0xF4, 0x60, 0x03};
uint16_t txBuf2[] = {0x80, 0x04, 0x77, 0xD6};// = {COMMAND_ADCV, 0xF46C};
uint16_t rxBuf[13];
uint16_t rxBuf2[4];
//memset(txBuf, 0, sizeof(txBuf));
//memset(txBuf2, 0, sizeof(txBuf2));
memset(rxBuf, 0, sizeof(rxBuf));
memset(rxBuf2, 0, sizeof(rxBuf2));
send_wakeup_signal();
//txBuf[0] = COMMAND_ADCV;
//txBuf[1] = 0xF46C;
// spiSendData(spiREG2, &data_config, 4, txBuf);
LTC6813_CS = 0;
SPI2_ReadWriteByte(txBuf[0]);//Send the read ID command
SPI2_ReadWriteByte(txBuf[1]);
SPI2_ReadWriteByte(txBuf[2]);
SPI2_ReadWriteByte(txBuf[3]);
LTC6813_CS = 1;
delay_os_ms(5);
send_wakeup_signal();
// //txBuf2[0] = cell_group;
// //txBuf2[1] = pec;
// spiSendData(spiREG2, &data_config, 4, txBuf2);
// spiGetData(spiREG2, &data_config, 13, rxBuf);
// //spiSendAndGetData(spiREG2, &data_config, 12, txBuf2, rxBuf);
// //spiTransmitAndReceiveData(spiREG2, &data_config, 12, txBuf2, cells);
LTC6813_CS = 0;
SPI2_ReadWriteByte(txBuf2[0]); // Send the read ID command
SPI2_ReadWriteByte(txBuf2[1]);
SPI2_ReadWriteByte(txBuf2[2]);
SPI2_ReadWriteByte(txBuf2[3]);
// Temp|=SPI2_ReadWriteByte(0xFF)<<8;
// Temp|=SPI2_ReadWriteByte(0xFF);
LTC6813_CS = 1;
// printf("RX: ");
// for (i = 0; i < 13; i++) printf("%X ", rxBuf[i]);
// printf("\n");
}
/**
* Sends a dummy byte to the LTC6804 in order to wake up
* the SPI interface.
*/
void send_wakeup_signal(void)
{
uint16_t txBuf[] = {0x00};
LTC6813_CS = 0;
SPI2_ReadWriteByte(txBuf[0]);
LTC6813_CS = 1;
delay_os_ms(5); // 5ms
}
/*************************************** EX Function **********************************************/
void ltc6813_wrcfg(uint8_t total_ic, //The number of ICs being written to
uint8_t w_config[][6] //A two dimensional array of the configuration data that will be written
)
{
const uint8_t BYTES_IN_REG = 6;
const uint8_t CMD_LEN = 4 + (8 * total_ic);
uint8_t *cmd = g_ltc_comm_buffer;
uint16_t cfg_pec;
uint8_t cmd_index; //command counter
if (total_ic > 2) return;
//cmd[0] & cmd[1] for WRCFGA command
cmd[0] = 0x00;
cmd[1] = 0x01;
//cmd[2] & cmd[3] for PEC0 & PEC1 respectively
cmd[2] = 0x3d;
cmd[3] = 0x6e;
cmd_index = 4;
for (uint8_t current_ic = total_ic; current_ic > 0; current_ic--) // executes for each ltc6813 in daisy chain, this loops starts with
{
// the last IC on the stack. The first configuration written is
// received by the last IC in the daisy chain
for (uint8_t current_byte = 0; current_byte < BYTES_IN_REG; current_byte++) // executes for each of the 6 bytes in the CFGR register
{
// current_byte is the byte counter
cmd[cmd_index] = w_config[current_ic - 1][current_byte]; //adding the config data to the array to be sent
cmd_index = cmd_index + 1;
}
cfg_pec = (uint16_t)pec15_calc(BYTES_IN_REG, &w_config[current_ic - 1][0]); // calculating the PEC for each ICs configuration register data
cmd[cmd_index] = (uint8_t)(cfg_pec >> 8);
cmd[cmd_index + 1] = (uint8_t)cfg_pec;
cmd_index = cmd_index + 2;
}
spi_write_array(CMD_LEN, cmd);
}
//Write the ltc6813 configuration 2 register
void ltc6813_wrcfg2(uint8_t total_ic, //The number of ICs being written to
uint8_t w_config[][6] //A two dimensional array of the configuration data that will be written
)
{
const uint8_t BYTES_IN_REG = 6;
const uint8_t CMD_LEN = 4 + (8 * total_ic);
uint8_t *cmd = g_ltc_comm_buffer;
uint16_t cfg_pec;
uint16_t cmd_pec;
uint8_t cmd_index; //command counter
if (total_ic > 2) return;
cmd[0] = 0x00;
cmd[1] = 0x24;
cmd_pec = pec15_calc(2, cmd);
cmd[2] = (uint8_t)(cmd_pec >> 8);
cmd[3] = (uint8_t)(cmd_pec);
cmd_index = 4;
for (uint8_t current_ic = total_ic; current_ic > 0; current_ic--) // executes for each ltc6813 in daisy chain, this loops starts with
{
// the last IC on the stack. The first configuration written is
// received by the last IC in the daisy chain
for (uint8_t current_byte = 0; current_byte < BYTES_IN_REG; current_byte++) // executes for each of the 6 bytes in the CFGR register
{
// current_byte is the byte counter
cmd[cmd_index] = w_config[current_ic-1][current_byte]; //adding the config data to the array to be sent
cmd_index = cmd_index + 1;
}
cfg_pec = (uint16_t)pec15_calc(BYTES_IN_REG, &w_config[current_ic-1][0]); // calculating the PEC for each ICs configuration register data
cmd[cmd_index] = (uint8_t)(cfg_pec >> 8);
cmd[cmd_index + 1] = (uint8_t)cfg_pec;
cmd_index = cmd_index + 2;
}
spi_write_array(CMD_LEN, cmd);
}
//Reads configuration registers of a ltc6813 daisy chain
int8_t ltc6813_rdcfg(uint8_t total_ic, //Number of ICs in the system
uint8_t r_config[][8] //A two dimensional array that the function stores the read configuration data.
)
{
const uint8_t BYTES_IN_REG = 8;
uint8_t cmd[4];
uint8_t *rx_data = g_ltc_comm_buffer;
int8_t pec_error = 0;
uint16_t data_pec;
uint16_t received_pec;
if (total_ic > 2) return -1;
cmd[0] = 0x00;
cmd[1] = 0x02;
cmd[2] = 0x2b;
cmd[3] = 0x0A;
spi_write_read(cmd, 4, rx_data, (BYTES_IN_REG * total_ic)); //Read the configuration data of all ICs on the daisy chain into
//rx_data[] array
for (uint8_t current_ic = 0; current_ic < total_ic; current_ic++) //executes for each ltc6813 in the daisy chain and packs the data
{
//into the r_config array as well as check the received Config data
//for any bit errors
for (uint8_t current_byte = 0; current_byte < BYTES_IN_REG; current_byte++)
{
r_config[current_ic][current_byte] = rx_data[current_byte + (current_ic*BYTES_IN_REG)];
}
received_pec = (r_config[current_ic][6]<<8) + r_config[current_ic][7];
data_pec = pec15_calc(6, &r_config[current_ic][0]);
if (received_pec != data_pec)
{
pec_error = -1;
}
}
return(pec_error);
}
received_pec = (r_config[current_ic][6]<<8) + r_config[current_ic][7];
data_pec = pec15_calc(6, &r_config[current_ic][0]);
if (received_pec != data_pec)
{
pec_error = -1;
}
}
return(pec_error);
}
received_pec = (r_config[current_ic][6]<<8) + r_config[current_ic][7];
data_pec = pec15_calc(6, &r_config[current_ic][0]);
if (received_pec != data_pec)
{
pec_error = -1;
}
}
return(pec_error);
}
//Reads configuration 2 registers of a ltc6813 daisy chain
int8_t ltc6813_rdcfg2(uint8_t total_ic, //Number of ICs in the system
uint8_t r_config[][8] //A two dimensional array that the function stores the read configuration data.
)
{
const uint8_t BYTES_IN_REG = 8;
uint8_t cmd[4];
uint8_t *rx_data = g_ltc_comm_buffer;
int8_t pec_error = 0;
uint16_t data_pec;
uint16_t cmd_pec;
uint16_t received_pec;
if (total_ic > 2) return -1;
cmd[0] = 0x00;
cmd[1] = 0x26;
cmd_pec = pec15_calc(2, cmd);
cmd[2] = (uint8_t)(cmd_pec >> 8);
cmd[3] = (uint8_t)(cmd_pec);
spi_write_read(cmd, 4, rx_data, (BYTES_IN_REG*total_ic)); //Read the configuration data of all ICs on the daisy chain into
for (uint8_t current_ic = 0; current_ic < total_ic; current_ic++) //executes for each ltc6813 in the daisy chain and packs the data
{
//into the r_config array as well as check the received Config data
//for any bit errors
for (uint8_t current_byte = 0; current_byte < BYTES_IN_REG; current_byte++)
{
r_config[current_ic][current_byte] = rx_data[current_byte + (current_ic*BYTES_IN_REG)];
}
received_pec = (r_config[current_ic][6]<<8) + r_config[current_ic][7];
data_pec = pec15_calc(6, &r_config[current_ic][0]);
printf("\n\rreceived PEC = %d data PEC = %d",received_pec,data_pec);
if (received_pec != data_pec)
{
pec_error = -1;
}
}
return(pec_error);
}

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/**
******************************************************************************
* @file battery_comm.h
* @author ESS Development Team
* @version V1.0.0
* @date 13/10/2019
* @brief This file contains all the functions prototypes for the battery_comm.c
* file.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2019 Amogreentech </center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef BATTERY_COMM_H_
#define BATTERY_COMM_H_
/* Includes ------------------------------------------------------------------*/
#include <stm32f10x.h>
/* Public function prototypes -----------------------------------------------*/
void init_battery_interface(void);
void App_TaskBatt(void);
void request_battery_voltage_A(uint16_t *cells);
void request_battery_voltage_B(uint16_t *cells);
void request_battery_voltage_C(uint16_t *cells);
void request_battery_voltage_D(uint16_t *cells);
void request_battery_voltage(uint16_t cell_group, uint16_t pec, uint16_t *cells);
#endif /* BATTERY_COMM_H_ */

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/**
******************************************************************************
* File Name : brtc.c
* Description : This file provides code for the configuration
* of board real time clock.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "brtc.h"
#include "includes.h"
#include "app_ver.h"
#include "asutil.h"
#include "device_param.h"
#include "dflash_sf1.h"
#include "io.h"
#include "alarm.h"
#include "ltc6813_comm.h"
#include "task_manager.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define RTC_TMR_PERIOD_TIME 10 // 10ms
#define WARMING_UP_TIME 5000 // 5sec
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
__IO uint32_t sub_sec = 0;
__IO uint32_t LocalTime = 0; /* this variable is used to create a time reference incremented by 10ms */
uint32_t WarmingUp = WARMING_UP_TIME;
OS_TMR RTC_TMR;
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
void Init_RTC(void)
{
OS_ERR err;
OSTmrCreate (&RTC_TMR,
"RTC Timer",
100,
1,
OS_OPT_TMR_PERIODIC,
(OS_TMR_CALLBACK_PTR)&Time_Update,
NULL,
&err);
OSTmrStart (&RTC_TMR,
&err);
}
uint32_t GetWarmingUp(void)
{
return WarmingUp;
}
void WarmingUp_Process(u16 tick)
{
if (WarmingUp > tick)
{
WarmingUp -= tick;
}
else
{
device_status.battery_status.bit.INIT = true;
}
}
uint32_t GetLocalTime(void)
{
return LocalTime;
}
void SetLocalTime(uint32_t nTime)
{
LocalTime = nTime;
sub_sec = 0;
clear_cb_value();
}
void Time_Update(void *ptmr, void *parg)
{
sub_sec += RTC_TMR_PERIOD_TIME;
if (sub_sec >= 1000)
{
LocalTime++;
sub_sec = 0;
}
WarmingUp_Process(RTC_TMR_PERIOD_TIME);
DecIOTaskTick(RTC_TMR_PERIOD_TIME);
dec_alarm_tick(RTC_TMR_PERIOD_TIME);
dec_cb_tick(RTC_TMR_PERIOD_TIME);
inc_afe_bufftime(RTC_TMR_PERIOD_TIME);
#ifdef CONSOLE_DEBUG
CalOSTaskCtxSwCtrPerSec(RTC_TMR_PERIOD_TIME);
#endif // #ifdef CONSOLE_DEBUG
IWDG_ReloadCounter();
}
/* Display Function *************************************************/
#ifdef CONSOLE_DEBUG
#endif // #ifdef CONSOLE_DEBUG

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/*****************************************************************************
*
* MSO Corporation
*
* File : rtc.h
* Compiler : IAR C 5.30C Kickstart
* Revision : $Revision: 1.0 $
* Date : $Date: 2010 / 7 / 16
* Updated by : $Author: Jongkwang Woo
*
* Support mail : spirit0305@naver.com
*
* Description : Header file for rtc.c
*
****************************************************************************/
#ifndef _BRTC_H_
#define _BRTC_H_
#include <stm32f10x.h>
void Init_RTC(void);
void Time_Update(void *ptmr, void *parg);
uint32_t GetLocalTime(void);
void SetLocalTime(uint32_t nTime);
#endif

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/**
******************************************************************************
* File Name : can_comm.c
* Description : This file provides code for the configuration
* of CAN communication.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include <includes.h>
#include "can.h"
#include "can_comm.h"
#include "can_data_process.h"
#include "can_inv_data_process.h"
#include "can_update_process.h"
#include "console.h"
#include "asutil.h"
#include "delay.h"
#include "device_param.h"
#include "brtc.h"
/* Private define ------------------------------------------------------------*/
#define CAN_TASK_TIME 1 // 20ms TASK
#define CAN_RX_TIMEOUT 500 // 500ms TimeOut
#define CAN_RX_DELAY 5
#define CAN_TX_DELAY 50
#define CAN_MAX_TIMEOUT 20
#define CAN_MAX_BUFFER_SIZE 512
/* Private typedef -----------------------------------------------------------*/
typedef struct
{
CanRxMsg Buffer;
u16 Tick;
u8 Current_ID;
u8 Mode;
u8 TxFlag;
u8 TxDetail;
u8 RxFlag;
u8 MsgPrint;
u8 DataPrint;
u8 BakMsgPrint;
u8 BakDataPrint;
} TCanConfig, *PCanConfig;
typedef struct _TCanCommState
{
u32 Tick;
u16 Timeout;
u8 Commfail;
u8 Init;
} TCanCommState, *PCanCommState;
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
TCanConfig CanConfig;
TCanCommState CanCommState;
CanRxMsg RxBuffer;
u8 CanBuzzerHold = false;
u8 CanParamSet = false;
u32 OldHeatbeat;
u32 curHsiTrimValue = 0x10;
u32 disHsiTrimValue;
extern uint32_t can_speed;
/* Private function prototypes -----------------------------------------------*/
void CanCommProcess(void);
void CanCommFailCheck(void);
void CanCommFailClear(void);
void CanSendData(void *data, u16 len);
void CanPacketInit(void);
u8 GetCanPacket(void);
void CanRxProcess(void);
void CanTxProcess(void);
void CanTxInitReqModule(void);
void CanTxParamReqModule(void);
void CanTxStatusPolling(u8 *aCmd);
void SendPacket(u32 SendId, u8 *data);
/* Private functions ---------------------------------------------------------*/
extern u8 FwData[];
extern u16 HostBalancingVoltage;
extern u16 HostBalancingVoltageDiff;
void CanCommInit(void)
{
switch (device_param.info.CanSpped) {
case 0: can_speed = 500000; break;
case 1: can_speed = 250000; break;
default: can_speed = 500000; break;
}
can1_init(can_speed);
memset(&CanConfig, 0x00, sizeof(TCanConfig));
memset(&CanCommState, 0x00, sizeof(TCanCommState));
CanCommState.Timeout = 500;
OldHeatbeat = device_value.Heartbeat;
}
/**
* @brief Initialize the Ethernet Module communication application
* @param None
* @retval None
*/
void App_TaskCanComm(void)
{
CanCommInit();
while (DEF_TRUE)
{
CanCommProcess();
delay_os_ms(CAN_TASK_TIME);
}
}
void CanCommProcess(void)
{
if (GetCanPacket() == SUCCESS)
{
CanRxProcess();
}
else
{
u32 aEsr = CAN1->ESR;
if ((aEsr & 0x0000000F) != 0x00)
can1_init(250000);
CanCommFailCheck();
delay_os_ms(5);
}
}
void CanRxProcess(void)
{
#ifdef CONSOLE_DEBUG
if ((CanConfig.MsgPrint == true)&&(screenmode == DIAG_MODE))
CAN_RX_DATA_PRINT(1, &RxBuffer);
#endif
switch (CheckCanPacket(&RxBuffer))
{
case 1: // F/W Update Packet
FwUpdateProcess(&RxBuffer);
break;
case 2: // Normal Comm. Packet
CanCommFailClear();
CanRxDataProcess(&RxBuffer);
break;
case 3: // Inventory Data Packet
CanRxInvDataProcess(&RxBuffer);
break;
}
}
void CanCommFailClear(void)
{
CanCommState.Commfail = false;
CanCommState.Tick = 0;
}
void CanCommFailCheck(void)
{
CanCommState.Tick++;
if (CanCommState.Tick > CanCommState.Timeout)
{
CanCommState.Tick = CanCommState.Timeout;
CanCommState.Commfail = true;
HostBalancingVoltage = 0;
HostBalancingVoltageDiff = 0;
}
}
void SendPacket(u32 SendId, u8 *data)
{
CanTxMsg sendobj;
sendobj.StdId = 0x0;
sendobj.ExtId = SendId;
sendobj.RTR = CAN_RTR_DATA;
sendobj.IDE = CAN_ID_EXT;
sendobj.DLC = 8;// data size
for (int i = 0; i < 8; i++)
{
sendobj.Data[i] = data[i];
}
CAN_SendPacket(&sendobj);
#ifdef CONSOLE_DEBUG
if ((CanConfig.DataPrint == true)&&(screenmode == DIAG_MODE))
CAN_TX_DATA_PRINT(1, &sendobj);
#endif
}
u8 GetCanPacket(void)
{
if (CAN_GetPacket(&RxBuffer) == SUCCESS)
return SUCCESS;
else
return ERROR;
}
#ifdef CONSOLE_DEBUG
void DDisplay_CanComm(u8 p)
{
if (p ||(CanConfig.BakMsgPrint != CanConfig.MsgPrint))
{
if (CanConfig.MsgPrint) GreenOutXY ( 27, 8, (u8 *)"ENABLE ");
else NormalOutXY( 27, 8, (u8 *)"DISABLE");
CanConfig.BakMsgPrint = CanConfig.MsgPrint;
}
if (p ||(CanConfig.BakDataPrint != CanConfig.DataPrint))
{
if (CanConfig.DataPrint)GreenOutXY ( 71, 8, (u8 *)"ENABLE ");
else NormalOutXY( 71, 8, (u8 *)"DISABLE");
CanConfig.BakDataPrint = CanConfig.DataPrint;
}
}
u8 DCanCommCommand(u8 cmd)
{
u8 result = 1;
switch (cmd)
{
case '2':
// CAN COMM MSG MONITOR
if (CanConfig.MsgPrint == true)
{
CanConfig.MsgPrint = false;
UserMessage("[MESSAGE]: CAN MSG PRINT DISABLE");
}
else
{
CanConfig.MsgPrint = true;
UserMessage("[MESSAGE]: CAN MSG PRINT ENABLE");
}
break;
case '3':
// CAN COMM DATA MONITOR
if (CanConfig.DataPrint == true)
{
CanConfig.DataPrint = false;
UserMessage("[MESSAGE]: CAN DATA PRINT DISABLE");
}
else
{
CanConfig.DataPrint = true;
UserMessage("[MESSAGE]: CAN DATA PRINT ENABLE");
}
break;
default:
result = 0;
break;
}
return result;
}
#endif // #ifdef CONSOLE_DEBUG
/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file can_comm.h
* @author MCD Application Team
* @version V1.0.0
* @date 05/12/2011
* @brief This file contains all the functions prototypes for the bscu_comm.c
* file.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _CAN_COMM_H_
#define _CAN_COMM_H_
/* Includes ------------------------------------------------------------------*/
#include <stm32f10x.h>
void App_TaskCanComm(void);
void App_TaskCanTxComm(void);
void SendPacket(u32 SendId, u8 *data);
void ODisplay_HsiCalValue(u8 p);
void DDisplay_CanComm(u8 p);
u8 DCanCommCommand(u8 cmd);
u8 GetCanCommState(void);
void CanBuzzerHoldCmd(void);
void CanParamSetCmd(void);
void CanParamSetReqLCD(void);
void CurrentNetInfoCmd(void);
u8 MakeCanParamSet(s16 id, s16 raddr, s16 rsize, s16 *rdata);
#endif
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

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/*****************************************************************************
*
* File : can_data_process.h
* Compiler : IAR C 5.10C Kickstart
* Revision : $Revision: 1.0 $
* Date : $Date: 2019 / 06 / 25
* Updated by : $Author: JK.Woo
*
* Support mail : spirit0305@naver.com
*
* Description : Header file for can_data_process.c
*
****************************************************************************/
#ifndef _CAN_DATA_PROCESS_H_
#define _CAN_DATA_PROCESS_H_
#include <stm32f10x.h>
typedef union
{
uint32_t LV;
struct
{
u32 SA : 8;
u32 PS : 8;
u32 PF : 8;
u32 DP : 1;
u32 R : 1;
u32 Index : 3;
u32 Rsvd : 3;
} BV;
} TCanHeader, *PCanHeader;
typedef union
{
uint32_t LV;
struct
{
uint32_t DID : 7; // Destination ID
uint32_t SID : 7; // Source ID
uint32_t NO : 8; // Number
uint32_t FC : 4; // Function Code
uint32_t PR : 3; // Priority
uint32_t Rsvd : 3;
} BV;
} TCanDLHeader, *PCanDLHeader;
u8 CheckCanAddr(u8 DstAddr);
u32 MakeCanTxExtId(u8 cmd, u8 flag);
s16 CheckCanPacket(CanRxMsg *data);
s16 CanRxDataProcess(CanRxMsg *data);
#endif

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/**
******************************************************************************
* File Name : can_inv_data_process.c
* Description : This file provides code for inventory data
* of CAN communication.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 Amogreentech Co., Ltd.
* All rights reserved.</center></h2>
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include <includes.h>
#include "can.h"
#include "can_comm.h"
#include "can_data_process.h"
#include "can_inv_data_process.h"
#include "app_ver.h"
#include "io.h"
#include "console.h"
#include "asutil.h"
#include "delay.h"
#include "device_param.h"
#include "brtc.h"
#include "dflash_cal.h"
#include "ltc6813_comm.h"
/* Define --------------------------------------------------------------------*/
// Function Code Define
// Request Code
#define CAN_REQ_SET_MANUFACTURE_DATE_CODE 1 // Must be get value and status
#define CAN_REQ_SET_SERIAL_NO1_CODE 2
#define CAN_REQ_SET_SERIAL_NO2_CODE 3
// Response Code
#define CAN_RSP_SET_MANUFACTURE_DATE_CODE 11
#define CAN_RSP_SET_SERIAL_NO1_CODE 21
#define CAN_RSP_SET_SERIAL_NO2_CODE 31
/* Private typedef -----------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
void CanRspManufactureDateCode(CanRxMsg *data); // CAN_REQ_SET_MANUFACTURE_DATE_CODE
void CanRspSerialNoCode(CanRxMsg *data, u8 type); // CAN_REQ_SET_SERIAL_NOx_CODE
/* External variables --------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
s16 CanRxInvDataProcess(CanRxMsg *data)
{
u8 dno = 0;
PCanHeader CanHeader;
CanHeader = (PCanHeader)(&data->ExtId);
dno = CheckCanAddr(CanHeader->BV.PS);
if (device_status.battery_status.bit.INIT == false)
return 0;
if (dno != GetDevAddr())
{
printf("\r\n DNO = %d, %d(%d)", dno, GetDevAddr(), CanHeader->BV.PF);
return 0;
}
switch (CanHeader->BV.PF)
{
case CAN_REQ_SET_MANUFACTURE_DATE_CODE: // Manufacuture Date
CanRspManufactureDateCode(data);
break;
case CAN_REQ_SET_SERIAL_NO1_CODE: // Serial No1
CanRspSerialNoCode(data, 0);
break;
case CAN_REQ_SET_SERIAL_NO2_CODE: // Serial No2
CanRspSerialNoCode(data, 1);
break;
}
return (dno);
}
void CanRspManufactureDateCode(CanRxMsg *data) // CAN_REQ_STATUS_CODE
{
u32 RspId, i;
u32 mDate = 0;
u8 RspData[8];
if (data->Data[7] == 0x01)
{
// ManufactureDate
mDate = (u32)((data->Data[0] << 24)
| (data->Data[1] << 16)
| (data->Data[2] << 8)
| (data->Data[3] << 0)
);
device_inv.ManufactureDate = mDate;
Save_Param();
Load_Param();
}
RspId = MakeCanTxExtId(CAN_RSP_SET_MANUFACTURE_DATE_CODE, 2);
memset(RspData, 0x00, sizeof(RspData));
i = 0;
RspData[i] = (u8)(device_inv.ManufactureDate >> 24); i++;
RspData[i] = (u8)(device_inv.ManufactureDate >> 16); i++;
RspData[i] = (u8)(device_inv.ManufactureDate >> 8); i++;
RspData[i] = (u8)(device_inv.ManufactureDate >> 0); i++;
i++;
i++;
i++;
RspData[i] = 1; i++;
SendPacket(RspId, RspData);
}
void CanRspSerialNoCode(CanRxMsg *data, u8 type) // CAN_REQ_SET_SERIAL_NOx_CODE
{
u32 RspId, sField;
u8 RspData[8];
if (data->Data[0] != 0xFF)
{
if (type == 0)
{
// Serial No 1
sField = 0;
for (int i = 0; i < 8; i++)
{
device_inv.SerialNo[sField + i] = data->Data[i];
}
}
else
{
// Serial No 2
sField = 8;
for (int i = 0; i < 8; i++)
{
device_inv.SerialNo[sField + i] = data->Data[i];
}
Save_Param();
}
}
if (type == 0)
RspId = MakeCanTxExtId(CAN_RSP_SET_SERIAL_NO1_CODE, 2);
else
RspId = MakeCanTxExtId(CAN_RSP_SET_SERIAL_NO2_CODE, 2);
memset(RspData, 0x00, sizeof(RspData));
for (int i = 0; i < 8; i++)
{
RspData[i] = device_inv.SerialNo[(type * 8) + i];
}
SendPacket(RspId, RspData);
}
/************************************** Data End **************************************/

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/**
******************************************************************************
* File Name : can_inv_data_process.c
* Description : This file provides code for the inventory data by CAN
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 Amogreentech Co., Ltd.
* All rights reserved.</center></h2>
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _CAN_INV_DATA_PROCESS_H_
#define _CAN_INV_DATA_PROCESS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stm32f10x.h>
/* Public defines */
/* Public Prototypes */
s16 CanRxInvDataProcess(CanRxMsg *data);
#ifdef __cplusplus
}
#endif
#endif /* _CAN_INV_DATA_PROCESS_H_ */

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/**
******************************************************************************
* File Name : can_update_process.c
* Description : This file provides code for the configuration
* of Firmware update by CAN communication.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include <includes.h>
#include "can.h"
#include "can_comm.h"
#include "can_data_process.h"
#include "console.h"
#include "asutil.h"
#include "device_param.h"
#include "flash_if.h"
#include "delay.h"
#include "io.h"
/* Define --------------------------------------------------------------------*/
#define CAN_MASTER_ADDR 0
// Function Code Define
#define DL_START_CODE 0 // Update Start Code
#define DL_SECTOR_ERASE_CODE 1 // Sector Erase Code
#define DL_SET_ADDRESS_CODE 2 // Flash Address Set Code
#define DL_READ_DATA_CODE 3 // Flash Data Read Code
#define DL_WRITE_DATA_CODE 4 // Flash Data Write Code
#define DL_WRITE_DATA_CSUM_CODE 5 // Flash Data Write Check Sum Code
#define DL_IMAGE_CSUM_CODE 6 // Flash Data Write Check Sum Code
#define DL_RESTART_CODE 7 // Restart
/* Private typedef -----------------------------------------------------------*/
typedef struct
{
uint32_t Flag;
uint32_t StratAddr;
uint32_t FileSize;
uint32_t WriteAddr;
uint32_t WriteLength;
uint32_t CurrentAddr;
uint32_t CurrentNumber;
uint32_t CheckSum32;
} TCanDLInfor, *PCanDLInfor;
TCanDLInfor CanDLInfor;
u8 FwData[2048];
/* Private functions ---------------------------------------------------------*/
void RspPacket(PCanDLHeader rhdr, u8 no, u8 *data);
uint32_t FwUpdateStartByCan(CanRxMsg *packet);
uint32_t SectorEraseProcessByCan(CanRxMsg *packet);
uint32_t WriteAddressSetByCan(CanRxMsg *packet);
uint32_t WriteDataByCan(CanRxMsg *packet);
uint32_t WriteDataChkSumByCan(CanRxMsg *packet);
uint32_t FwImageChkSumByCan(CanRxMsg *packet);
uint32_t UpdateRestartByCan(CanRxMsg *packet);
/**
* @brief Firmware Update Process
* @param CAN Message
* @retval Result
*/
s16 FwUpdateProcess(CanRxMsg *data)
{
u16 dno = 0;
s16 result = false;
PCanDLHeader CanHeader;
CanHeader = (PCanDLHeader)(&data->ExtId);
dno = CanHeader->BV.DID;
if (dno != GetDevAddr())
{
return 0;
}
switch (CanHeader->BV.FC)
{
case DL_START_CODE: // Firmware update start
result = FwUpdateStartByCan(data);
break;
case DL_SECTOR_ERASE_CODE: // Sector Erase
result = SectorEraseProcessByCan(data);
break;
case DL_SET_ADDRESS_CODE: // Set Write Address and Length
result = WriteAddressSetByCan(data);
break;
case DL_WRITE_DATA_CODE: // Write data
result = WriteDataByCan(data);
break;
case DL_WRITE_DATA_CSUM_CODE: // Check packet checksum
result = WriteDataChkSumByCan(data);
break;
case DL_IMAGE_CSUM_CODE: // Check firmware image checksum
result = FwImageChkSumByCan(data);
break;
case DL_RESTART_CODE: // Restart option
result = UpdateRestartByCan(data);
break;
}
return result;
}
uint32_t FwUpdateStartByCan(CanRxMsg *packet)
{
uint32_t result = 0;
uint8_t sdata[8];
uint32_t flen;
flen = (uint32_t)((packet->Data[4] << 24)
| (packet->Data[5] << 16)
| (packet->Data[6] << 8)
| (packet->Data[7] << 0)
);
// printf("\r\nStart Fw Update : V%d.%d.%d.%d, %d bytes"
// , packet->Data[0]
// , packet->Data[1]
// , packet->Data[2]
// , packet->Data[3]
// , flen);
if (flen <= mBMS_FW_MAX_SIZE)
{
fwinfo.AppVer[0] = packet->Data[0];
fwinfo.AppVer[1] = packet->Data[1];
fwinfo.AppVer[2] = packet->Data[2];
fwinfo.AppVer[3] = packet->Data[3];
fwinfo.AppFileSize = flen;
fwinfo.AppUpdate = 1;
}
else
result = 2;
for (int i = 0; i < 8; i++)
{
sdata[i] = 0x00;
}
sdata[7] = result;
RspPacket((PCanDLHeader)(&packet->ExtId), 0, sdata);
return result;
}
uint32_t SectorEraseProcessByCan(CanRxMsg *packet)
{
uint32_t result = 0;
uint8_t sdata[8];
uint32_t sector_addr;
if ((fwinfo.AppUpdate == 1) ||(fwinfo.AppUpdate == 2))
{
sector_addr = (uint32_t)((packet->Data[0] << 24)
| (packet->Data[1] << 16)
| (packet->Data[2] << 8)
| (packet->Data[3] << 0));
// printf("\r\nsector_addr = 0x%08X", sector_addr);
if ((sector_addr >= mBMS_FW_ADDRESS) && (sector_addr <= mBMS_FW_END_ADDRESS))
{
if (fwinfo.AppFileSize <= 0xC000)
{
FLASH_If_Erase(sector_addr, fwinfo.AppFileSize);
if (result == 0)
fwinfo.AppUpdate = 2;
}
else
result = 3;
}
else
result = 2;
}
else
result = 9;
for (int i = 0; i < 8; i++)
{
sdata[i] = packet->Data[i];
}
sdata[7] = result;
RspPacket((PCanDLHeader)(&packet->ExtId), 0, sdata);
return result;
}
uint32_t WriteAddressSetByCan(CanRxMsg *packet)
{
uint32_t result = 0;
uint8_t sdata[8];
uint32_t waddr, wlen;
waddr = (uint32_t)((packet->Data[0] << 24)
| (packet->Data[1] << 16)
| (packet->Data[2] << 8)
| (packet->Data[3] << 0));
wlen = (uint32_t)((packet->Data[4] << 24)
| (packet->Data[5] << 16)
| (packet->Data[6] << 8)
| (packet->Data[7] << 0));
if ((waddr >= mBMS_FW_ADDRESS) && (waddr < mBMS_FW_END_ADDRESS))
{
// printf("\r\nwrite_data = 0x%08X (%d bytes)", waddr, wlen);
if ((wlen > 0) && (wlen <= 256))
{
CanDLInfor.WriteAddr = waddr;
CanDLInfor.WriteLength = wlen;
}
else
result = 2;
}
else
result = 1;
for (int i = 0; i < 8; i++)
{
sdata[i] = 0x00;
}
sdata[7] = result;
RspPacket((PCanDLHeader)(&packet->ExtId), 0, sdata);
return result;
}
uint32_t WriteDataByCan(CanRxMsg *packet)
{
uint32_t result = 0;
PCanDLHeader CanHeader;
CanHeader = (PCanDLHeader)(&packet->ExtId);
uint32_t base = CanDLInfor.WriteAddr + (CanHeader->BV.NO * 8);
result = FLASH_If_Write(&base, (uint32_t*)packet->Data, 8 / 4);
return result;
}
uint32_t WriteDataChkSumByCan(CanRxMsg *packet)
{
uint32_t result = 0;
uint8_t sdata[8] = {0};
uint32_t waddr = 0;
uint32_t rsum, csum = 0;
int len = CanDLInfor.WriteLength * 8;
for (int i = 0; i < len; i++)
{
// csum += FwData[i];
csum += *(uint8_t *)(CanDLInfor.WriteAddr + i);
}
waddr = (uint32_t)((packet->Data[0] << 24)
| (packet->Data[1] << 16)
| (packet->Data[2] << 8)
| (packet->Data[3] << 0)
);
rsum = (uint32_t)((packet->Data[4] << 24)
| (packet->Data[5] << 16)
| (packet->Data[6] << 8)
| (packet->Data[7] << 0)
);
// printf("\r\nWriteDataChkSumByCan: 0x%08X, 0x%08X (0x%08X) 0x%08X (%d)", csum, rsum, waddr, CanDLInfor.WriteAddr, len);
if (csum == rsum)
{
if ((waddr >= mBMS_FW_ADDRESS) && (waddr <= (mBMS_FW_END_ADDRESS - 0x800)))
{
if (CanDLInfor.WriteAddr == waddr)
waddr += len;
else
result = 3;
}
else
{
result = 4;
}
}
else
{
result = 5;
}
sdata[0] = (uint8_t)(waddr >> 24);
sdata[1] = (uint8_t)(waddr >> 16);
sdata[2] = (uint8_t)(waddr >> 8);
sdata[3] = (uint8_t)(waddr >> 0);
sdata[7] = result;
RspPacket((PCanDLHeader)(&packet->ExtId), 0, sdata);
return result;
}
uint32_t FwImageChkSumByCan(CanRxMsg *packet)
{
uint32_t result = 0;
uint8_t sdata[8] = {0};
uint32_t rsize = 0;
uint32_t rsum, csum = 0;
uint8_t *base = (uint8_t *)mBMS_FW_ADDRESS;
int len = fwinfo.AppFileSize;
rsize = (uint32_t)((packet->Data[0] << 24)
| (packet->Data[1] << 16)
| (packet->Data[2] << 8)
| (packet->Data[3] << 0)
);
rsum = (uint32_t)((packet->Data[4] << 24)
| (packet->Data[5] << 16)
| (packet->Data[6] << 8)
| (packet->Data[7] << 0)
);
if (rsize == len)
{
for (int i = 0; i < len; i++)
csum += base[i];
if (csum == rsum)
fwinfo.AppUpdate = 3;
else
result = 2;
}
else
result = 1;
sdata[7] = result;
RspPacket((PCanDLHeader)(&packet->ExtId), 0, sdata);
return result;
}
uint32_t UpdateRestartByCan(CanRxMsg *packet)
{
uint32_t result = 0;
uint8_t sdata[8] = {0};
uint32_t reset = 0;
switch (packet->Data[0])
{
case 0:
break;
case 1:
reset = 1;
break;
case 2:
break;
case 3:
fwinfo.AppUpdate = 9;
SaveFwInfo();
reset = 1;
break;
}
sdata[7] = result;
RspPacket((PCanDLHeader)(&packet->ExtId), 0, sdata);
if (reset)
{
delay_os_ms(1000);
Sys_Soft_Reset();
}
return result;
}
void RspPacket(PCanDLHeader rhdr, u8 no, u8 *data)
{
TCanDLHeader shdr;
shdr.BV.PR = 4;
shdr.BV.FC = rhdr->BV.FC;
shdr.BV.NO = no;
shdr.BV.SID = rhdr->BV.DID;
shdr.BV.DID = rhdr->BV.SID;
SendPacket(shdr.LV, data);
}
/************************************** TX Data End **************************************/

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/*****************************************************************************
*
* File : can_update_process.h
* Compiler : IAR C 5.10C Kickstart
* Revision : $Revision: 1.0 $
* Date : $Date: 2019 / 06 / 25
* Updated by : $Author: JK.Woo
*
* Support mail : spirit0305@naver.com
*
* Description : Header file for can_update_process.c
*
****************************************************************************/
#ifndef _CAN_UPDATE_PROCESS_H_
#define _CAN_UPDATE_PROCESS_H_
#include <stm32f10x.h>
s16 FwUpdateProcess(CanRxMsg *data);
#endif

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/**
******************************************************************************
* File Name : console.c
* Description : This file provides code for the configuration
* of debug console.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#ifdef CONSOLE_DEBUG
#include "screen.h"
#endif
#include "includes.h"
#include "console.h"
#include "delay.h"
#include "app_ver.h"
#include "usart.h"
#include "asutil.h"
#include "display_status.h"
#include "dflash_sf1.h"
#include "dflash_sbs.h"
#include "can_comm.h"
#include "ltc6813_comm.h"
#include "device_param.h"
#include "io.h"
#include "task_manager.h"
#include "can.h"
#include "brtc.h"
#include "temp.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
s8 screenmode;
u8 position;
u32 BakOSCtxSwCtr; /* Counter of number of context switches */
u32 BakLocalTime; /* this variable is used to create a time reference incremented by 10ms */
u8 console_text[128];
u8 display_text[81];
/* Private prototype functions -----------------------------------------------*/
void DebugConsole(void);
void Console(u8 *one);
void Prompt(void);
s8 Process_Data(u8 *text, u16 size);
s8 Process_DataSet(u8 *text, u16 size);
s8 Process_CurrentDataSet(u8 *text, u16 size);
s8 Process_DataDiagnostic(u8 *text, u16 size);
s8 Process_DataNetSet(u8 *text, u16 size);
s8 Process_OSStatus(u8 *text, u16 size);
s8 Process_Inventory_Data(u8 *text, u16 size);
s8 Process_DataChgCtrlCfgSet(u8 *text, u16 size);
extern void ff_process(void);
void Console_Initial(void)
{
position = 0;
screenmode = OP_MODE;
}
void AppTaskDebug(void)
{
Init_RTC();
Load_Param();
ADC_Param_Load();
#ifdef CONSOLE_DEBUG
Console_Initial();
#endif
while (DEF_TRUE)
{
#ifdef CONSOLE_DEBUG
DebugConsole();
#endif
device_value.Heartbeat = GetLocalTime();
/* Reload IWDG counter */
IWDG_ReloadCounter();
delay_os_ms(1);
}
}
#ifdef CONSOLE_DEBUG
u16 debug_recv_data(u8 *data)
{
u16 len = 0;
if (UART1_GetChar(data) == SUCCESS) len = 1;
return len;
}
void DebugConsole(void)
{
u8 one[20];
u16 i, len;
len = debug_recv_data(one);
for (i = 0; i < len; i++)
Console(&one[i]);
DisplayScreen(false);
}
void Console(u8 *one)
{
u8 i, ok;
ok = 0;
switch (one[0])
{
case 0x0d: /* ENTER(CR)값 */
if (position == 0)
{
ViewScreen();
Prompt(); /* Prompt 출력 */
position = 0;
for (i = 0; i < 80; i++) console_text[i] = 0x00;
break;
}
switch (screenmode)
{
case OP_MODE: /* operating state */
ok = Process_Data(console_text, position);
if (!ok) {UserMessage(" [Invalid Command]");}
break;
case SET_MODE: /* setting state */
ok = Process_DataSet(console_text, position);
if (!ok) {UserMessage(" [Invalid Command]");}
break;
case OS_STATUS_MODE: /* OS Status */
ok = Process_OSStatus(console_text, position);
if (!ok) {UserMessage(" [Invalid Command]");}
break;
case DIAG_MODE: /* diagnostic */
ok = Process_DataDiagnostic(console_text, position);
if (!ok) {UserMessage(" [Invalid Command]");}
break;
case SF1_MODE:
ok = Process_DataSF1Set(console_text, position);
if (!ok) {UserMessage(" [Invalid Command]");}
break;
case SBS_MODE:
ok = Process_DataSBSSet(console_text, position);
if (!ok) {UserMessage(" [Invalid Command]");}
break;
default:
screenmode = OP_MODE;
break;
}
Prompt();
position = 0;
for (i = 0; i < 80; i++) console_text[i] = 0x00;
break;
case 0x08: /* BACKSPACE(BS) 값 */
case 0x7F: /* BACKSPACE(BS) 값 */
if (position > 0)
{
printf("%c %c", 0x08, 0x08);
position--;
}
break;
case 0x0A: /* enter */
break;
default :
if (one[0] >= 0x20)
{
printf("%c", one[0]);
if (position < 80)
{
console_text[position++] = one[0];
console_text[position] = 0x00;
}
else
{
position = 0;
Prompt();
for (i = 0; i < 80; i++) console_text[i] = 0x00;
}
}
break;
}
}
/* OPERATING STATE에서 명령어 처리 */
s8 Process_Data(u8 *text, u16 size) /* console_text[0]=0x00, size =0 (default) */
{
int ret;
if(size > 1)
{
if(text[1] != ' ') return(0); /* 첫칸에 space 포함되어있으면 Invalid command */
}
text[size] = 0x00;
ret = 1;
switch (text[0])
{
case 's':
screenmode = SET_MODE;
ViewScreen();
break;
case 'd':
screenmode = DIAG_MODE;
ViewScreen();
break;
default:
ret = 0;
break;
}
return(ret);
}
/* SETTING STATE 에서 명령어 처리 */
s8 Process_DataSet(u8 *text, u16 size)
{
u16 ret;
/* 첫 칸에 space가 포함되어 있으면 invalid command */
if (size > 1)
if (text[1] != ' ') return(0);
text[size] = 0x00;
ret = 1;
switch (text[0])
{
case 'o': /* operating state로 전환 */
screenmode = OP_MODE;
ViewScreen();
break;
case 'd': /* diagnostic mode로 전환 */
screenmode = DIAG_MODE;
ViewScreen();
break;
case 'z':
screenmode = OS_STATUS_MODE;
ViewScreen();
break;
case '1':
screenmode = SF1_MODE;
ViewScreen();
break;
case '2':
screenmode = SBS_MODE;
ViewScreen();
break;
case '!': /* INIT */
Param_Init(true, false);
Save_Param();
break;
default :
ret = 0;
break;
}
return(ret);
}
// OPERATING STATE에서 명령어 처리
s8 Process_OSStatus(u8 *text, u16 size) // console_text[0]=0x00, size =0 (default)
{
int ret;
if (size > 1)
if (text[1] != ' ') return(0); /* 첫칸에 space 포함되어있으면 Invalid command */
text[size] = 0x00;
ret = 1;
switch (text[0])
{
case 'o':
screenmode = OP_MODE;
ViewScreen();
break;
case 's':
screenmode = SET_MODE;
ViewScreen();
break;
case 'd':
screenmode = DIAG_MODE;
ViewScreen();
break;
default:
ret = 0;
break;
}
return(ret);
}
extern void Vref2Print(void);
/* diagnostic mode 에서 명령어 처리 */
s8 Process_DataDiagnostic(u8 *text, u16 size)
{
s8 ret, i;
text[size] = 0x00;
ret = 1;
switch (text[0])
{
case 'o': /* operating mode로 전환 */
screenmode = OP_MODE;
ViewScreen();
break;
case 's': /* setting status로 전환 */
screenmode = SET_MODE;
ViewScreen();
break;
case 'G' : /* Memory Dump */
if (size > 2)
dump_mem(TextToAddr((u8 *)&text[2]));
break;
case '2':
case '3':
// CAN COMM MONITOR
ret = DCanCommCommand(text[0]);
break;
case '1':
// case '2':
// case '3':
case '4':
case '5':
case '6':
i = SetLtc6813_Param(&text[2],text[0]);
if (i == 0)
UserMessage("COMMAND COMPLETE");
else if (i == 1)
UserMessage("COMMAND FORMAT ERROR"); /* setting format오류 */
else
UserMessage("COMMAND LIMIT ERROR"); /* setting 한계값오류 */
break;
case 'q': /* Exit Application */
UserMessage("Exit Application ? (Y or N)");
switch (WaitUserCMD((u8 *)"YyNn"))
{
case 1:
case 2:
UserMessage("System Reset !!");
Sys_Soft_Reset();
while(1);
case 3:
case 4:
UserMessage("Exit Application Cancel !!");
break;
default:
UserMessage("Command Timeout !!");
break;
}
break;
default :
ret = 0;
break;
}
return(ret);
}
/* Inventor Mode STATE에서 명령어 처리 */
s8 Process_Inventory_Data(u8 *text, u16 size)
{
s8 ret;
if (size > 1)
{
if(text[1] != ' ') return(0); /* 첫칸에 space 포함되어있으면 Invalid command */
}
text[size] = 0x00;
ret = 1;
switch (text[0])
{
case 'o':
screenmode = OP_MODE;
ViewScreen();
break;
case 's':
screenmode = SET_MODE;
ViewScreen();
break;
case 'd':
screenmode = DIAG_MODE;
ViewScreen();
break;
case '1': // H/W Version Set
case '2': // Serial Number Parameter Setting
case '3': // Manufacturer Date Parameter Setting
case '4': // Install Date Parameter Setting
break;
default:
ret = 0;
break;
}
return(ret);
}
void Prompt()
{
u8 ver[4];
switch (screenmode)
{
case 0 :
case 1 :
case 2 :
case 3 :
case 4 :
case 5 :
case 6 :
case 7 :
case 8 :
case 9 :
case 10 :
case 11 :
case 12 :
case 13 :
case 14 :
case 21 :
case 22 :
case 23 :
case 24 :
case 25 :
case 26 :
case 27 :
case 28 :
case 29 :
case 30 :
case 31 :
case 32 :
case 33 :
case 34 :
case 40 :
case 41 :
case 100 :
case 101 :
GetAppVersion(ver);
printf("%1c[%02d;%02dH", 0x1b, 23, 1);
printf("%s %d.%d.%d.%d>"
, BD_MODEL
, ver[0]
, ver[1]
, ver[2]
, ver[3]
);
break;
case GUI_MODE:
break;
default :
GetAppVersion(ver);
printf("%s %d.%d.%d.%d>"
, BD_MODEL
, ver[0]
, ver[1]
, ver[2]
, ver[3]
);
break;
}
}
void DisplayScreen(u8 p)
{
switch(screenmode)
{
case OP_MODE:
ODisplayDevice(p);
ODisplayBalancingValue(p);
ODisplayAdcStatus(p);
break;
case SET_MODE:
break;
case OS_STATUS_MODE:
osDisplayTaskStatus(p);
break;
case DIAG_MODE:
DDisplay_CanComm(p);
break;
case SF1_MODE:
SF1Display(p);
break;
case SBS_MODE:
SBSDisplay(p);
break;
}
}
void ViewScreen() /* Screen Mode에 따른 바탕 화면 출력 */
{
ClearConsol();
switch (screenmode)
{
case OP_MODE : /* View Status */
APPVerDisplay();
OmodeScreen();
break;
case SET_MODE : /* View Setting Status */
SmodeScreen();
break;
case OS_STATUS_MODE: /* View OS Task Status */
OSmodeScreen();
break;
case DIAG_MODE: /* View Diagnostic Status */
DmodeScreen();
break;
case SF1_MODE:
SF1modeScreen();
break;
case SBS_MODE:
SBSmodeScreen();
break;
default :
printf("UNDEFINE SCREEN MODE");
screenmode = 0;
break;
}
DisplayScreen(true);
}
#endif // #ifdef CONSOLE_DEBUG

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/**
******************************************************************************
* File Name : console.h
* Description : This file provides code for the configuration
* of debug console.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
#ifndef _CONSOLE_H_
#define _CONSOLE_H_
#include <stm32f10x.h>
#define OP_MODE 0
#define SET_MODE 1
#define DIAG_MODE 2
#define OS_STATUS_MODE 9
#define SF1_MODE 21
#define SBS_MODE 22
#define TEST_MODE 100
#define GUI_MODE -1
#define RX_PRINT 0
#define TX_PRINT 1
extern s8 screenmode;
extern u8 position;
extern u32 BakOSCtxSwCtr; /* Counter of number of context switches */
extern u32 BakLocalTime; /* this variable is used to create a time reference incremented by 10ms */
void AppTaskDebug(void);
u16 debug_recv_data(u8 *data);
void ViewScreen(void);
void DisplayScreen(u8 p);
void Console_Initial(void);
void Console(u8 *one);
#endif

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/* Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* High Level description:
* http://www.ti.com/lit/ds/symlink/device.pdf
* Thechnical Reference:
* http://www.ti.com/lit/ug/sluu431/sluu431.pdf
*/
#include "includes.h"
#include "device_param.h"
#include "flash_if.h"
#include "dflash_sf1.h"
#include "dflash_cal.h"
#include "dflash_sbs.h"
#include "asutil.h"
#define PARAM_INIT_DATA 0xAAAA32F6
TDEVICE_VALUE device_value, dis_device_value;
TDEVICE_STATUS device_status, dis_device_status;
TDEVICE_PARAM device_param, dis_device_param;
TDEVICE_INV device_inv, dis_device_inv;
int CellQty = 21;
int TempQty = 8;
void SetCellQuantity(u8 cQuantity)
{
if ((cQuantity > 0) && (cQuantity <= 21))
{
device_param.info.CellQuantity = cQuantity;
Save_Param();
}
}
void SetCanSpeed(uint8_t Speed)
{
device_param.info.CanSpped = Speed;
Save_Param();
}
void Param_Init(u8 flag, u8 factory)
{
SF1_InitData();
if (factory == true)
{
SBS_InitData();
}
}
void Load_Param(void)
{
uint32_t len = sizeof(TDEVICE_PARAM);
if ((len % 4) > 0) len = len / 4 + 1;
else len = len / 4;
memcpy(&device_param, (uint8_t *)mBMS_PARAM_BASE_ADDR, (len * 4));
memcpy(&device_inv, (uint8_t *)(mBMS_PARAM_BASE_ADDR + (len * 4)), sizeof(TDEVICE_INV));
if (device_param.initdata != PARAM_INIT_DATA)
{
device_param.initdata = PARAM_INIT_DATA;
// Parameter init
Param_Init(true, true);
Save_Param();
}
else if ((device_param.info.DevAddr == 0) || (device_param.info.DevAddr > DEVICE_MAX_ADDR))
{
SBS_InitData();
Save_Param();
}
}
void Save_Param(void)
{
uint32_t result = 0;
uint32_t sector_addr = mBMS_PARAM_BASE_ADDR;
result = FLASH_If_Erase(sector_addr, PAGE_SIZE);
if (result == 0)
{
uint32_t base = (uint32_t)&device_param;
uint32_t len = sizeof(TDEVICE_PARAM);
if ((len % 4) > 0) len = len / 4 + 1;
else len = len / 4;
result = FLASH_If_Write(&sector_addr, (uint32_t *)base, len);
#ifdef CONSOLE_DEBUG
if (result != 0)
printf("\r\n Param save fail (%d)", result);
#endif
sector_addr = mBMS_PARAM_BASE_ADDR + (len * 4);
base = (uint32_t)&device_inv;
len = sizeof(TDEVICE_INV);
if ((len % 4) > 0) len = len / 4 + 1;
else len = len / 4;
result = FLASH_If_Write(&sector_addr, (uint32_t *)base, len);
#ifdef CONSOLE_DEBUG
if (result != 0)
printf("\r\n Inventory data save fail (%d)", result);
#endif
}
}
void LoadFwInfo(void)
{
memcpy(&fwinfo, (uint8_t *)mBMS_FW_INFO_BASE_ADDR, sizeof(FW_INFO));
}
void SaveFwInfo(void)
{
uint32_t result = 0;
uint32_t sector_addr = mBMS_FW_INFO_BASE_ADDR;
result = FLASH_If_Erase(sector_addr, PAGE_SIZE);
if (result == 0)
{
uint32_t base = (uint32_t)&fwinfo;
uint32_t len = sizeof(FW_INFO);
if ((len % 4) > 0)
len = len / 4 + 1;
else
len = len / 4;
result = FLASH_If_Write(&sector_addr, (uint32_t *)base, len);
if (result != 0)
printf("\r\n Fw information save fail (%d)", result);
}
}

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/*****************************************************************************
*
* File : device.h
* Compiler : IAR C 6.30
* Revision : $Revision: 1.0 $
* Date : $Date: 2015 / 03 / 13
* Updated by : $Author: Jongkwang Woo
*
* Support mail : spirit0305@naver.com
*
* Description : Header file for device.c
*
****************************************************************************/
#ifndef _DEVICE_PARAM_H_
#define _DEVICE_PARAM_H_
#include <stm32f10x.h>
#include <stdint.h>
#define DEVICE_NAME "PR-67150S"
#define DEVICE_TYPE 64150
#define DEVICE_REV "1.2"
#define DEVICE_MAX_ADDR 22
#define DEVICE_MAX_CELL 24
#define DEVICE_MAX_TEMP 8
#define CELL_DIV_UNIT 10000
#define BIT(x) (unsigned short)(0x0001 << x)
#define BIT32(x) (unsigned long)(0x00000001 << x)
typedef union {
u16 value;
struct {
u16 DSG_S : 1; // LSB 0 // Dischage Fet Control
u16 CHG_S : 1; // LSB 1 // Charge Fet Control
u16 DCP : 1; // LSB 2 // Pre-charge Fet Control
u16 RXM : 1; // LSB 3
u16 FD : 1; // LSB 4
u16 FC : 1; // LSB 5
u16 MD : 1; // LSB 6
u16 INIT : 1; // LSB 7
u16 DSG_C : 1; // MSB 8 // Dischage Fet Status
u16 CHG_C : 1; // MSB 9 // Charge Fet Status
u16 ZVC_C : 1; // MSB 10 // Pre-charge Fet Status
u16 CB : 1; // MSB 11 // Cell Balancing Flag
u16 AFE : 1; // MSB 12 // AFE PL455 Comm Status
u16 TDA : 1; // MSB 13
u16 TCA : 1; // MSB 14
u16 ACB : 1; // MSB 15
} bit;
} TBATTERY_STATUS, *pBATTERY_STATUS;
typedef struct {
u16 voltage[DEVICE_MAX_CELL]; // Offset 0 ; 2bytes * (24) = 48bytes
struct {
struct {
u16 value; // Offset 0 ; 2bytes
u16 num; // Offset 2 ; 2bytes
} Max, Min; // Offset 0 ; 4bytes + 4bytes = 8bytes
u16 avg; // Offset 8 ; 2bytes
u16 diff; // Offset 10 ; 2bytes
} avg; // Offset 48 ; 12bytes
} TCELL_STATUS, *PCELL_STATUS; // 60bytes
typedef struct
{
s16 temperature[DEVICE_MAX_TEMP]; // Offset 0 ; 2bytes * (8) = 16bytes
struct
{
struct
{
s16 value; // Offset 0 ; 2bytes
u16 num; // Offset 2 ; 2bytes
} Max, Min; // Offset 0 ; 4bytes + 4bytes = 8bytes
s16 avg; // Offset 8 ; 2bytes
s16 diff; // Offset 10 ; 2bytes
} avg; // Offset 36 ; 12bytes
} TTEMP_STATUS, *PTEMP_STATUS; // 28bytes
typedef struct
{
struct
{
u16 value;
u16 num;
} Max, Min;
u16 avg;
u16 diff;
} TAVG_VALUE, *PAVG_VALUE;
typedef struct
{
u16 value;
u16 num;
} TVoltMinMax, *PVoltMinMax;
typedef struct
{
s16 value;
u16 num;
} TTempMinMax, *PTempMinMax;
typedef struct
{
u32 Heartbeat; // Offset 0
u32 ManufactureDate; // Offset 4
u32 FwVersion; // Offset 8
u32 RemainingCapacity; // Offset 12
u32 CycleCount; // Offset 16
u32 BatVoltage; // Offset 20
u32 BatSumVoltage; // Offset 24
s16 Current; // Offset 28
u16 RelativeStateOfCharge; // Offset 30
u16 StateOfHealth; // Offset 32
TCELL_STATUS Cell;
TTEMP_STATUS Temp;
} TDEVICE_VALUE, *PDEVICE_VALUE;
typedef union
{
u16 value;
struct
{
u16 over_voltage : 1; // 0x0001
u16 cell_over_voltage : 1; // 0x0002
u16 under_voltage : 1; // 0x0004
u16 cell_under_voltage : 1; // 0x0008
u16 chg_over_current : 1; // 0x0010
u16 dsg_over_current : 1; // 0x0020
u16 reserved1 : 2; //
u16 chg_high_temp : 1; // 0x0100
u16 dsg_high_temp : 1; // 0x0200
u16 chg_low_temp : 1; // 0x0400
u16 dsg_low_temp : 1; // 0x0800
u16 low_capacity : 1; // 0x1000
u16 reserved2 : 1; //
u16 cell_voltage_diff : 1; //
u16 reserved3 : 1; //
} bit;
} TWarning;
typedef union
{
u16 value;
struct
{
u16 over_voltage : 1; // 0x0001
u16 cell_over_voltage : 1; // 0x0002
u16 under_voltage : 1; // 0x0004
u16 cell_under_voltage : 1; // 0x0008
u16 chg_over_current : 1; // 0x0010
u16 dsg_over_current : 1; // 0x0020
u16 reserved1 : 2; //
u16 chg_high_temp : 1; // 0x0100
u16 dsg_high_temp : 1; // 0x0200
u16 chg_low_temp : 1; // 0x0400
u16 dsg_low_temp : 1; // 0x0800
u16 reserved2 : 1; // 0x1000
u16 short_circuit : 1; // 0x2000
u16 cell_voltage_diff : 1; // 0x4000
u16 afe_fail : 1; // 0x8000
} bit;
} TProtection;
typedef union {
u32 value;
struct {
u32 cell_00 : 1;
u32 cell_01 : 1;
u32 cell_02 : 1;
u32 cell_03 : 1;
u32 cell_04 : 1;
u32 cell_05 : 1;
u32 cell_06 : 1;
u32 cell_07 : 1;
u32 cell_08 : 1;
u32 cell_09 : 1;
u32 cell_10 : 1;
u32 cell_11 : 1;
u32 cell_12 : 1;
u32 cell_13 : 1;
u32 cell_14 : 1;
u32 cell_15 : 1;
u32 cell_16 : 1;
u32 cell_17 : 1;
u32 cell_18 : 1;
u32 cell_19 : 1;
u32 cell_20 : 1;
u32 cell_21 : 1;
u32 cell_22 : 1;
u32 cell_23 : 1;
u32 cell_24 : 1;
u32 cell_25 : 1;
u32 cell_26 : 1;
u32 cell_27 : 1;
u32 cell_28 : 1;
u32 cell_29 : 1;
u32 cell_flag : 1;
u32 reserved : 1;
} bit;
} TCellBalanceData, *PCellBalanceData;
typedef union {
u32 value;
struct {
u32 ch_00 : 1;
u32 ch_01 : 1;
u32 ch_02 : 1;
u32 ch_03 : 1;
u32 ch_04 : 1;
u32 ch_05 : 1;
u32 ch_06 : 1;
u32 ch_07 : 1;
u32 ch_08 : 1;
u32 ch_09 : 1;
u32 ch_10 : 1;
u32 ch_11 : 1;
u32 ch_12 : 1;
u32 ch_13 : 1;
u32 ch_14 : 1;
u32 ch_15 : 1;
u32 ch_16 : 1;
u32 ch_17 : 1;
u32 ch_18 : 1;
u32 ch_19 : 1;
u32 ch_flag : 1;
u32 reserved : 11;
} bit;
} TBalanceEnable, *PBalanceEnable;
typedef union
{
u32 uValue;
struct
{
u32 cell0 : 1;
u32 cell1 : 1;
u32 cell2 : 1;
u32 cell3 : 1;
u32 cell4 : 1;
u32 cell5 : 1;
u32 cell6 : 1;
u32 cell7 : 1;
u32 cell8 : 1;
u32 cell9 : 1;
u32 cell10 : 1;
u32 cell11 : 1;
u32 cell12 : 1;
u32 cell13 : 1;
u32 cell14 : 1;
u32 cell15 : 1;
u32 cell16 : 1;
u32 cell17 : 1;
u32 cell18 : 1;
u32 cell19 : 1;
u32 cell20 : 1;
u32 reserved : 11;
} Bit;
} TCELL_BIT, *PCELL_BIT;
typedef union
{
u16 uValue;
struct {
u16 temp0 : 1;
u16 temp1 : 1;
u16 temp2 : 1;
u16 temp3 : 1;
u16 temp4 : 1;
u16 temp5 : 1;
u16 temp6 : 1;
u16 temp7 : 1;
u16 reserved : 8;
} Bit;
} TTEMP_BIT, *PTEMP_BIT;
typedef struct
{
TBATTERY_STATUS battery_status; // 2 16 bit
u16 op_status; // 4 16 bit
u16 alarm_status; // 6 16 bit
TWarning warning; // 8 16 bit
TProtection protection; // 10 16 bit
u16 auto_balancing; // 12 16 bit
TCellBalanceData cellbalance; // 16 32 bit
TBalanceEnable balance_enable; // 20 32 bit
TCELL_BIT cov_warning_cell; // 24 32 bit
TCELL_BIT cov_protection_cell; // 24 32 bit
TCELL_BIT cuv_warning_cell; // 28 32 bit
TCELL_BIT cuv_protection_cell; // 32 32 bit
TTEMP_BIT otd_warning_temp; // 34 16 bit
TTEMP_BIT otd_protection_temp; // 36 16 bit
TTEMP_BIT otc_warning_temp; // 38 16 bit
TTEMP_BIT otc_protection_temp; // 40 16 bit
TTEMP_BIT ltd_warning_temp; // 42 16 bit
TTEMP_BIT ltd_protection_temp; // 44 16 bit
TTEMP_BIT ltc_warning_temp; // 46 16 bit
TTEMP_BIT ltc_protection_temp; // 48 16 bit
} TDEVICE_STATUS, *PDEVICE_STATUS;
typedef struct
{
u16 Reserved[7];
u16 CanSpped;
s16 CvOffset[2];
u16 DevAddr;
u16 CellQuantity;
} TDEVICE_INFO, *PDEVICE_INFO;
#pragma pack(2)
typedef struct
{
u16 COV_Threshold; // ST COV Threshold (Offset 0)
u16 COV_Warning; // ST COV Warning (Offset 2)
u16 COV_Recovery; // ST COV Recovery (Offset 4)
u16 CUV_Threshold; // CUV Threshold (Offset 6)
u16 CUV_Warning; // CUV Warning (Offset 8)
u16 CUV_Recovery; // CUV Recovery (Offset 10)
u16 SOV_Threshold; // ST COV Threshold (Offset 0)
u16 SOV_Warning; // ST COV Warning (Offset 2)
u16 SOV_Recovery; // ST COV Recovery (Offset 4)
u16 SUV_Threshold; // CUV Threshold (Offset 6)
u16 SUV_Warning; // CUV Warning (Offset 8)
u16 SUV_Recovery; // CUV Recovery (Offset 10)
} TDEVICE_PARAM_VOLTAGE_VALUE, *PDEVICE_PARAM_VOLTAGE_VALUE;
// C.2.3 Temperature (Subclass 690)
typedef struct
{
s16 OT_Chg_Threshold; // (Offset 0) 0.1C
s16 OT_Chg_Warning; // (Offset 2) 0.1C
s16 OT_Chg_Recovery; // (Offset 6) 0.1C
s16 OT_Dsg_Threshold; // (Offset 8) 0.1C
s16 OT_Dsg_Warning; // (Offset 10) 0.1C
s16 OT_Dsg_Recovery; // (Offset 14) 0.1C
s16 LT_Chg_Threshold; // (Offset 16) 0.1C
s16 LT_Chg_Warning; // (Offset 18) 0.1C
s16 LT_Chg_Recovery; // (Offset 22) 0.1C
s16 LT_Dsg_Threshold; // (Offset 16) 0.1C
s16 LT_Dsg_Warning; // (Offset 18) 0.1C
s16 LT_Dsg_Recovery; // (Offset 22) 0.1C
s16 Open_Thermistor; // Open Thermistor (Offset 24)
s16 Recovery_Thermistor; // Recovery Thermistor (Offset 26)
} TDEVICE_PARAM_TEMPERATURE_VALUE, *PDEVICE_PARAM_TEMPERATURE_VALUE;
typedef struct
{
u16 Cell_Voltage_Diff_Threshold; // (Offset 0) mV
u16 Cell_Voltage_Diff_Warning; // (Offset 2) mV
u16 Cell_Voltage_Diff_Recovery; // (Offset 4) mV
u16 Cell_Voltage_Diff_Time; // (Offset 6) Sec
} TDEVICE_PARAM_CELL_VOLTAGE_DIFF_VALUE, *PDEVICE_PARAM_CELL_VOLTAGE_DIFF_VALUE;
typedef struct
{
TDEVICE_PARAM_VOLTAGE_VALUE voltage;
TDEVICE_PARAM_TEMPERATURE_VALUE temperature;
TDEVICE_PARAM_CELL_VOLTAGE_DIFF_VALUE cv_diff;
} TDEVICE_PARAM_SAFETY_VALUE, *PDEVICE_PARAM_SAFETY_VALUE;
typedef struct
{
s16 Cell_Balance_Threshold; // (Offset 0) mV
s16 Cell_Balance_Window; // (Offset 2) mV
s16 Cell_Balance_Min; // (Offset 4) mV
s16 Cell_Balance_Interval; // (offset 6) S
} TDEVICE_CHG_CTRL_CFG_CELL_BAL_CFG_VALUE, *PDEVICE_CHG_CTRL_CFG_CELL_BAL_CFG_VALUE;
typedef struct _TDEVICE_CHG_CTRL_VALUE
{
TDEVICE_CHG_CTRL_CFG_CELL_BAL_CFG_VALUE cell_bal_cfg;
} TDEVICE_CHG_CTRL_VALUE, *PDEVICE_CHG_CTRL_VALUE;
typedef struct
{
uint32_t initdata;
TDEVICE_INFO info;
TDEVICE_PARAM_SAFETY_VALUE safety;
TDEVICE_CHG_CTRL_VALUE chg_ctrl;
} TDEVICE_PARAM, *PDEVICE_PARAM;
typedef struct
{
/* Time of testing and calibration data, NOT the factory out day. Local time in seconds since 2000.
Ex:
Epoch time offset (1 January 2000 00:00:00) = 946684800
Current epoch time (1 October 2019 12:00:00) = 1569931200
Timestamp = 1569931200 - 946684800 = 623246400
(Used 'https://www.epochconverter.com/' for conversion)
*/
u32 ManufactureDate;
u8 SerialNo[16]; // BMU18SAYYMMNNNN
u8 ModuleNo[16]; //
} TDEVICE_INV, *PDEVICE_INV;
// Setting value
typedef struct _TDEVICE_SET_VALUE
{
u8 Flag;
u8 Busy;
u16 SubClass;
u16 Offset;
u16 Size;
u16 Value;
} TDEVICE_SET_VALUE, *PDEVICE_SET_VALUE;
extern TDEVICE_VALUE device_value, dis_device_value;
extern TDEVICE_STATUS device_status, dis_device_status;
extern TDEVICE_PARAM device_param, dis_device_param;
extern TDEVICE_INV device_inv;
extern int CellQty;
extern int TempQty;
void Load_Param(void);
void Save_Param(void);
void LoadFwInfo(void);
void SaveFwInfo(void);
void SetCanSpeed(uint8_t Speed);
void Param_Init(u8 flag, u8 factory);
#pragma pack()
#endif

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/* Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* High Level description:
* http://www.ti.com/lit/ds/symlink/bq28400.pdf
* Thechnical Reference:
* http://www.ti.com/lit/ug/sluu431/sluu431.pdf
*/
#include "includes.h"
#include "dflash_cal.h"
#include "console.h"
#include "asutil.h"
#include "device_param.h"
u8 SetCal_Param(u8 *text, u8 aDevice);
u8 SetCal_Param1(u8 *text, u8 aDevice);
s32 CalibrationVoltage(u16 voltage, u8 item)
{
s32 sum = 0;
float a, b, result;
// switch (item)
// {
// case DSG_CURR_ID:
// sum = GetRealCurrentAdc(item) + device_param.cal.current.DC_Offset;
// break;
// case CHG_CURR_ID:
// sum = GetRealCurrentAdc(item) + device_param.cal.current.CC1_Offset;
// break;
// }
a = (float)voltage / 100;
b = (float)sum / 10000;
result = a / b;
return (s32)(result * 1000);
}
s32 CalibrationCurrentA(u16 current, u8 item)
{
s32 sum;
float a, b, result;
switch (item)
{
// case DSG_CURR_ID:
// sum = GetRealCurrentSum() - device_param.cal.current.DC_Offset;
// break;
// case CHG_CURR_ID:
// sum = GetRealCurrentSum() - device_param.cal.current.CC1_Offset;
// break;
}
if (sum < 0) sum *= -1;
a = (float)current / 100;
b = (float)(sum) / 10000;
result = a / b;
return (s32)(result * 1000);
}
#ifdef CONSOLE_DEBUG
/* SETTING STATE 에서 명령어 처리 */
s8 Process_DataCalSet(u8 *text, u16 size)
{
u16 i, ret;
/* 첫 칸에 space가 포함되어 있으면 invalid command */
if (size > 1) {if (text[1] != ' ') return(0);}
text[size] = 0x00;
ret = 1;
switch (text[0])
{
case 'o': /* operating state로 전환 */
screenmode = OP_MODE;
ViewScreen();
break;
case 's': /* diagnostic mode로 전환 */
screenmode = SET_MODE;
ViewScreen();
break;
case 'd': /* diagnostic mode로 전환 */
screenmode = DIAG_MODE;
ViewScreen();
break;
case '1': // OCV Alarm Parameter Setting
case '2': // OCV Shutdown Parameter Setting
case '3': // OCV Alarm Parameter Setting
case '4': // OCV Shutdown Parameter Setting
case '5': // OCV Shutdown Parameter Setting
case '6': // OCV Shutdown Parameter Setting
i = SetCal_Param(&text[2],text[0]);
if (i == 0)
UserMessage("COMMAND COMPLETE");
else if (i == 1)
UserMessage("COMMAND FORMAT ERROR"); /* setting format오류 */
else
UserMessage("COMMAND LIMIT ERROR"); /* setting 한계값오류 */
break;
case '7':
case '8':
case '9':
case 'A':
case 'B':
case 'C':
case 'K' : // Charge Current Calibration
i = SetCal_Param1(&text[2], text[0]);
if (i == 0)
UserMessage("COMMAND COMPLETE");
else if (i == 1)
UserMessage("COMMAND FORMAT ERROR"); /* setting format오류 */
else
UserMessage("COMMAND LIMIT ERROR"); /* setting 한계값오류 */
break;
case 'I':
Cal_InitData();
Save_Param();
break;
default :
ret = 1;
break;
}
return(ret);
}
u8 SetCal_Param(u8 *text, u8 aDevice)
{
u16 size, i, j;
s16 aParam[4];
s32 bParam[4];
u8 temp[10];
u8 ret;
u8 cmd;
ret = 0;
size = 0;
while (text[size] != 0x00) size++; /* text의 전체 문자열 size 측정 */
switch (aDevice)
{
case '1': // Cal_Voltage_Subclass
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
aParam[0] = StrToInt(temp, j); /* Value */
switch (cmd)
{
case '1': device_param.cal.voltage.Cell_Scale_0 = aParam[0]; break;
case '2': device_param.cal.voltage.Cell_Scale_1 = aParam[0]; break;
case '3': device_param.cal.voltage.BAT_Gain = aParam[0]; break;
case '4': device_param.cal.voltage.BAT_Offset = aParam[0]; break;
default : return (1);
}
Save_Param();
break;
case '2': // Cal_Discharge_Current_Subclass
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
bParam[0] = StrToInt32(temp, j); /* Value */
switch (cmd)
{
case '1': device_param.cal.current.DC_Gain = bParam[0]; break;
case '2': device_param.cal.current.DC_Offset = bParam[0]; break;
default: return(1);
}
Save_Param();
break;
case '3': // Cal_Charge_Current_Subclass
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
bParam[0] = StrToInt32(temp, j); /* Value */
switch (cmd)
{
case '1': device_param.cal.current.CC1_Gain = bParam[0]; break;
case '2': device_param.cal.current.CC1_Offset = bParam[0]; break;
case '3': device_param.cal.current.CC2_Gain = bParam[0]; break;
case '4': device_param.cal.current.CC2_Offset = bParam[0]; break;
default: return(1);
}
Save_Param();
break;
case '6': // Current Offset (Subclass 20)
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
aParam[0] = StrToInt(temp, j); /* Value */
switch (cmd)
{
case '1': device_param.cal.current_offset.Int_Power = aParam[0]; break;
case '2': device_param.cal.current_offset.Relay_Power = aParam[0]; break;
default: return(1);
}
Save_Param();
break;
default:
ret = 1;
break;
}
return(ret); /* setting value 정상 */
}
u8 SetCal_Param1(u8 *text, u8 aDevice)
{
u8 temp[20];
float fParam[2];
u16 i, j, size;
u8 ret;
ret = 0;
size = 0;
while (text[size] != 0x00) size++; /* text의 전체 문자열 size 측정 */
switch (aDevice)
{
case '8' : // Discharge Current Calibration
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
temp[j] = 0x00;
i = i + j + 1;
fParam[0] = atof((char *)temp); /* IP a */
device_param.cal.current.DC_Gain = CalibrationVoltage((u16)(fParam[0] * 100), DSG_CURR_ID);
Save_Param();
break;
case '9' : // Charge Current Calibration
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
temp[j] = 0x00;
i = i + j + 1;
fParam[0] = atof((char *)temp); /* IP a */
if ((device_param.sbs.data.Spec_Info & 0x8000) != 0)
device_param.cal.current.CC1_Gain = CalibrationVoltage((u16)(fParam[0] * 100), CHG_CURR_ID);
else
device_param.cal.current.CC2_Gain = CalibrationVoltage((u16)(fParam[0] * 100), CHG_CURR_ID);
Save_Param();
break;
case 'K' : // Charge Current Calibration
device_param.cal.current.DC_Offset = -GetRealCurrentAdc(DSG_CURR_ID);
device_param.cal.current.CC1_Offset = -GetRealCurrentAdc(CHG_CURR_ID);
device_param.cal.current.CC2_Offset = -GetRealCurrentAdc(CHG_CURR_ID);
Save_Param();
break;
case 'B' : // Discharge Current Calibration
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
temp[j] = 0x00;
i = i + j + 1;
fParam[0] = atof((char *)temp); /* IP a */
device_param.cal.current.DC_Gain = CalibrationCurrentA((u16)(fParam[0] * 100), DSG_CURR_ID);
Save_Param();
break;
case 'C' : // Charge Current Calibration
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
temp[j] = 0x00;
i = i + j + 1;
fParam[0] = atof((char *)temp); /* IP a */
if ((device_param.sbs.data.Spec_Info & 0x8000) != 0)
device_param.cal.current.CC1_Gain = CalibrationCurrentA((u16)(fParam[0] * 100), CHG_CURR_ID);
else
device_param.cal.current.CC2_Gain = CalibrationCurrentA((u16)(fParam[0] * 100), CHG_CURR_ID);
Save_Param();
break;
default:
ret = 1;
break;
}
return(ret); /* setting value 정상 */
}
void CalDisplayVoltage(u8 p)
{
u8 text[20];
// Cell_Scale_0 (Offset 0)
if (p || (dis_device_param.cal.voltage.Cell_Scale_0 != device_param.cal.voltage.Cell_Scale_0))
{
sprintf((char *)text, "%5d", device_param.cal.voltage.Cell_Scale_0);
GreenOutXY(19, 3, text);
dis_device_param.cal.voltage.Cell_Scale_0 = device_param.cal.voltage.Cell_Scale_0;
}
// Cell_Scale_1 (Offset 2)
if (p || (dis_device_param.cal.voltage.Cell_Scale_1 != device_param.cal.voltage.Cell_Scale_1))
{
sprintf((char *)text, "%5d", device_param.cal.voltage.Cell_Scale_1);
GreenOutXY(19, 4, text);
dis_device_param.cal.voltage.Cell_Scale_1 = device_param.cal.voltage.Cell_Scale_1;
}
// Pack_Offset (Offset 8)
if (p || (dis_device_param.cal.voltage.BAT_Gain != device_param.cal.voltage.BAT_Gain))
{
sprintf((char *)text, "%5d", device_param.cal.voltage.BAT_Gain);
GreenOutXY(19, 5, text);
dis_device_param.cal.voltage.BAT_Gain = device_param.cal.voltage.BAT_Gain;
}
// BAT_Offset (Offset 10)
if (p || (dis_device_param.cal.voltage.BAT_Offset != device_param.cal.voltage.BAT_Offset))
{
sprintf((char *)text, "%5d", device_param.cal.voltage.BAT_Offset);
GreenOutXY(19, 6, text);
dis_device_param.cal.voltage.BAT_Offset = device_param.cal.voltage.BAT_Offset;
}
}
void CalDisplayDischargeCurrent(u8 p)
{
u8 text[20];
u16 x;
x = 18;
// DC_Gain (Offset 0)
if (p || (dis_device_param.cal.current.DC_Gain != device_param.cal.current.DC_Gain))
{
sprintf((char *)text, "%8d", device_param.cal.current.DC_Gain);
GreenOutXY(x, 8, text);
dis_device_param.cal.current.DC_Gain = device_param.cal.current.DC_Gain;
}
// DC_Offset (Offset 4)
if (p || (dis_device_param.cal.current.DC_Offset != device_param.cal.current.DC_Offset))
{
sprintf((char *)text, "%8d", device_param.cal.current.DC_Offset);
GreenOutXY(x, 9, text);
dis_device_param.cal.current.DC_Offset = device_param.cal.current.DC_Offset;
}
}
void CalDisplayChargeCurrent(u8 p)
{
u8 text[20];
u16 x;
x = 18;
// CC1_Gain (Offset 0)
if (p || (dis_device_param.cal.current.CC1_Gain != device_param.cal.current.CC1_Gain))
{
sprintf((char *)text, "%8d", device_param.cal.current.CC1_Gain);
GreenOutXY(x, 11, text);
dis_device_param.cal.current.CC1_Gain = device_param.cal.current.CC1_Gain;
}
// CC1_Offset (Offset 4)
if (p || (dis_device_param.cal.current.CC1_Offset != device_param.cal.current.CC1_Offset))
{
sprintf((char *)text, "%8d", device_param.cal.current.CC1_Offset);
GreenOutXY(x, 12, text);
dis_device_param.cal.current.CC1_Offset = device_param.cal.current.CC1_Offset;
}
x = 18;
// CC2_Gain (Offset 0)
if (p || (dis_device_param.cal.current.CC2_Gain != device_param.cal.current.CC2_Gain))
{
sprintf((char *)text, "%8d", device_param.cal.current.CC2_Gain);
GreenOutXY(x, 14, text);
dis_device_param.cal.current.CC2_Gain = device_param.cal.current.CC2_Gain;
}
// CC2_Offset (Offset 4)
if (p || (dis_device_param.cal.current.CC2_Offset != device_param.cal.current.CC2_Offset))
{
sprintf((char *)text, "%8d", device_param.cal.current.CC2_Offset);
GreenOutXY(x, 15, text);
dis_device_param.cal.current.CC2_Offset = device_param.cal.current.CC2_Offset;
}
}
void CalDisplayPwrConsumpt(u8 p)
{
u8 text[20];
u16 x;
x = 46;
// Internal Power Consumption (Offset 0)
if (p || (dis_device_param.cal.current_offset.Int_Power != device_param.cal.current_offset.Int_Power))
{
sprintf((char *)text, "%5d", device_param.cal.current_offset.Int_Power);
GreenOutXY(x, 3, text);
dis_device_param.cal.current_offset.Int_Power = device_param.cal.current_offset.Int_Power;
}
// Relay Power Consumption (Offset 0)
if (p || (dis_device_param.cal.current_offset.Relay_Power != device_param.cal.current_offset.Relay_Power))
{
sprintf((char *)text, "%5d", device_param.cal.current_offset.Relay_Power);
GreenOutXY(x, 4, text);
dis_device_param.cal.current_offset.Relay_Power = device_param.cal.current_offset.Relay_Power;
}
}
void CalDisplay(u8 p)
{
CalDisplayVoltage(p);
CalDisplayChargeCurrent(p);
CalDisplayDischargeCurrent(p);
CalDisplayPwrConsumpt(p);
}
#endif // #ifdef CONSOLE_DEBUG
void Cal_InitData(void)
{
device_param.cal.voltage.Cell_Scale_0 = 0;
device_param.cal.voltage.Cell_Scale_1 = 0;
device_param.cal.voltage.BAT_Gain = 0; // (1/1000)
device_param.cal.voltage.BAT_Offset = 0; // (1/10000)
device_param.cal.current.CC1_Gain = 0;
device_param.cal.current.CC1_Offset = 0;
device_param.cal.current.CC2_Gain = 0;
device_param.cal.current.CC2_Offset = 0;
device_param.cal.current.DC_Gain = 0;
device_param.cal.current.DC_Offset = 0;
device_param.cal.current_offset.Int_Power = 100;
device_param.cal.current_offset.Relay_Power = 0;
}

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/*****************************************************************************
*
* File : dflash_cfg.h
* Compiler : IAR C 6.30
* Revision : $Revision: 1.0 $
* Date : $Date: 2015 / 03 / 13
* Updated by : $Author: Jongkwang Woo
*
* Support mail : spirit0305@naver.com
*
* Description : Header file for dflash_cfg.c
*
****************************************************************************/
#ifndef _DFLASH_CAL_H_
#define _DFLASH_CAL_H_
#include <stm32f10x.h>
s8 Process_DataCalSet(u8 *text, u16 size);
void CalDisplay(u8 p);
void Cal_InitData(void);
s32 CalibrationVoltage(u16 voltage, u8 item);
s32 CalibrationCurrentA(u16 current, u8 item);
#endif

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/* Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* High Level description:
* http://www.ti.com/lit/ds/symlink/bq28400.pdf
* Thechnical Reference:
* http://www.ti.com/lit/ug/sluu431/sluu431.pdf
*/
#include "includes.h"
#include "dflash_sbs.h"
#include "console.h"
#include "asutil.h"
#include "device_param.h"
#ifdef CONSOLE_DEBUG
u8 SSet_SbsCfg(u8 *text, u8 aDevice);
/* SETTING STATE 에서 명령어 처리 */
s8 Process_DataSBSSet(u8 *text, u16 size)
{
u16 i, ret;
/* 첫 칸에 space가 포함되어 있으면 invalid command */
if (size > 1) {if (text[1] != ' ') return(0);}
text[size] = 0x00;
ret = 1;
switch (text[0])
{
case 'o': /* operating state로 전환 */
screenmode = OP_MODE;
ViewScreen();
break;
case 's': /* diagnostic mode로 전환 */
screenmode = SET_MODE;
ViewScreen();
break;
case 'd': /* diagnostic mode로 전환 */
screenmode = DIAG_MODE;
ViewScreen();
break;
case '1': // SBS Data Parameter Setting
case '2': // SBS Data Parameter Setting
i = SSet_SbsCfg(&text[2],text[0]);
if (i == 0)
UserMessage("COMMAND COMPLETE");
else if (i == 1)
UserMessage("COMMAND FORMAT ERROR"); /* setting format오류 */
else
UserMessage("COMMAND LIMIT ERROR"); /* setting 한계값오류 */
break;
case 'I':
SBS_InitData();
Save_Param();
break;
default :
ret = 0;
break;
}
return(ret);
}
u8 SSet_SbsCfg(u8 *text, u8 aDevice)
{
u16 size, i, j;
s16 aParam[4];
u8 temp[10];
u8 ret;
u8 cmd;
ret = 0;
size = 0;
while (text[size] != 0x00) size++; /* text의 전체 문자열 size 측정 */
switch (aDevice)
{
case '1': // Data
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
switch (cmd)
{
case '1': aParam[0] = StrToInt(temp, j); break; /* Int Value */
}
switch (cmd)
{
case '1': device_param.info.DevAddr = aParam[0]; break;
default : return (1);
}
Save_Param();
break;
case '2': // Data
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
switch (cmd)
{
case '1': aParam[0] = StrToInt(temp, j); break; /* Int Value */
case '2': aParam[0] = StrToInt(temp, j); break; /* Int Value */
}
switch (cmd)
{
case '1': device_param.info.CvOffset[0] = aParam[0]; break;
case '2': device_param.info.CvOffset[1] = aParam[0]; break;
default : return (1);
}
Save_Param();
break;
default:
ret = 1;
break;
}
return(ret); /* setting value 정상 */
}
void SBSDisplayData(u8 p)
{
u8 text[20];
// Initial_Battery_Mode (Offset 0)
if (p || (dis_device_param.info.DevAddr != device_param.info.DevAddr))
{
sprintf((char *)text, "%4d", device_param.info.DevAddr);
GreenOutXY(20, 3, text);
dis_device_param.info.DevAddr = device_param.info.DevAddr;
}
// Cell Voltage Offset - LSB
if (p || (dis_device_param.info.CvOffset[0] != device_param.info.CvOffset[0]))
{
sprintf((char *)text, "%4d", device_param.info.CvOffset[0]);
GreenOutXY(20, 5, text);
dis_device_param.info.CvOffset[0] = device_param.info.CvOffset[0];
}
// Cell Voltage Offset - MSB
if (p || (dis_device_param.info.CvOffset[1] != device_param.info.CvOffset[1]))
{
sprintf((char *)text, "%4d", device_param.info.CvOffset[1]);
GreenOutXY(20, 6, text);
dis_device_param.info.CvOffset[1] = device_param.info.CvOffset[1];
}
}
void SBSDisplay(u8 p)
{
SBSDisplayData(p);
}
#endif // #ifdef CONSOLE_DEBUG
void SBS_InitData(void)
{
device_param.info.DevAddr = 1;
device_param.info.CvOffset[0] = 0;
device_param.info.CvOffset[1] = 0;
}

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/*****************************************************************************
*
* File : dflash_cfg.h
* Compiler : IAR C 6.30
* Revision : $Revision: 1.0 $
* Date : $Date: 2015 / 03 / 13
* Updated by : $Author: Jongkwang Woo
*
* Support mail : spirit0305@naver.com
*
* Description : Header file for dflash_sbs.c
*
****************************************************************************/
#ifndef _DFLASH_SBS_H_
#define _DFLASH_SBS_H_
#include <stm32f10x.h>
s8 Process_DataSBSSet(u8 *text, u16 size);
void SBSDisplay(u8 p);
void SBS_InitData(void);
#endif

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/* Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* High Level description:
* http://www.ti.com/lit/ds/symlink/bq28400.pdf
* Thechnical Reference:
* http://www.ti.com/lit/ug/sluu431/sluu431.pdf
*/
#include "includes.h"
#include "dflash_sf1.h"
#include "device_param.h"
#include "asutil.h"
#include "console.h"
#ifdef CONSOLE_DEBUG
u8 SetSF1_Param(u8 *text, u8 aDevice);
/* SETTING STATE 에서 명령어 처리 */
s8 Process_DataSF1Set(u8 *text, u16 size)
{
u16 i, ret;
/* 첫 칸에 space가 포함되어 있으면 invalid command */
if (size > 1) {if (text[1] != ' ') return(0);}
text[size] = 0x00;
ret = 1;
switch (text[0])
{
case 'o': /* operating state로 전환 */
screenmode = OP_MODE;
ViewScreen();
break;
case 's': /* diagnostic mode로 전환 */
screenmode = SET_MODE;
ViewScreen();
break;
case 'd': /* diagnostic mode로 전환 */
screenmode = DIAG_MODE;
ViewScreen();
break;
case 'z':
screenmode = OS_STATUS_MODE;
ViewScreen();
break;
case '1': // Cell Voltage Parameter Setting
case '2': // Current Parameter Setting
case '3': // Temperature Parameter Setting
case '4': // System Voltage Parameter Setting
case '5': // SOC Parameter Setting
case '6': // Open Thermistor Parameter Setting
i = SetSF1_Param(&text[2],text[0]);
if (i == 0)
UserMessage("COMMAND COMPLETE");
else if (i == 1)
UserMessage("COMMAND FORMAT ERROR"); /* setting format오류 */
else
UserMessage("COMMAND LIMIT ERROR"); /* setting 한계값오류 */
break;
case 'I':
SF1_InitData();
Save_Param();
break;
default :
ret = 0;
break;
}
return(ret);
}
void SF1DisplayCellVoltage(u8 p)
{
u8 text[20];
PDEVICE_PARAM param = &device_param;
PDEVICE_PARAM dis_param = &dis_device_param;
int x;
x = 20;
// COV Threshold (Offset 0)
if (p || (dis_param->safety.voltage.COV_Threshold != param->safety.voltage.COV_Threshold))
{
sprintf((char *)text, "%4d", param->safety.voltage.COV_Threshold);
GreenOutXY(x, 4, text);
dis_param->safety.voltage.COV_Threshold = param->safety.voltage.COV_Threshold;
}
// COV Warning (Offset 2)
if (p || (dis_param->safety.voltage.COV_Warning != param->safety.voltage.COV_Warning))
{
sprintf((char *)text, "%4d", param->safety.voltage.COV_Warning);
GreenOutXY(x, 5, text);
dis_param->safety.voltage.COV_Warning = param->safety.voltage.COV_Warning;
}
// COV Recovery (Offset 4)
if (p || (dis_param->safety.voltage.COV_Recovery != param->safety.voltage.COV_Recovery))
{
sprintf((char *)text, "%4d", param->safety.voltage.COV_Recovery);
GreenOutXY(x, 6, text);
dis_param->safety.voltage.COV_Recovery = param->safety.voltage.COV_Recovery;
}
// CUV Threshold (Offset 6)
if (p || (dis_param->safety.voltage.CUV_Threshold != param->safety.voltage.CUV_Threshold))
{
sprintf((char *)text, "%4d", param->safety.voltage.CUV_Threshold);
GreenOutXY(x, 8, text);
dis_param->safety.voltage.CUV_Threshold = param->safety.voltage.CUV_Threshold;
}
// CUV Warning (Offset 8)
if (p || (dis_param->safety.voltage.CUV_Warning != param->safety.voltage.CUV_Warning))
{
sprintf((char *)text, "%4d", param->safety.voltage.CUV_Warning);
GreenOutXY(x, 9, text);
dis_param->safety.voltage.CUV_Warning = param->safety.voltage.CUV_Warning;
}
// CUV Recovery (Offset 10)
if (p || (dis_param->safety.voltage.CUV_Recovery != param->safety.voltage.CUV_Recovery))
{
sprintf((char *)text, "%4d", param->safety.voltage.CUV_Recovery);
GreenOutXY(x, 10, text);
dis_param->safety.voltage.CUV_Recovery = param->safety.voltage.CUV_Recovery;
}
}
void SF1DisplayTemperature(u8 p)
{
PDEVICE_PARAM param = &device_param;
PDEVICE_PARAM dis_param = &dis_device_param;
int x;
x = 46;
// Over Temp Chg Threshold (Offset 0)
if (p || (dis_param->safety.temperature.OT_Chg_Threshold != param->safety.temperature.OT_Chg_Threshold))
{
FloatNormalOutIntXY(x, 4, (float)param->safety.temperature.OT_Chg_Threshold / 10, 5, 1);
dis_param->safety.temperature.OT_Chg_Threshold = param->safety.temperature.OT_Chg_Threshold;
}
// Over Temp Chg Warning (Offset 2)
if (p || (dis_param->safety.temperature.OT_Chg_Warning != param->safety.temperature.OT_Chg_Warning))
{
FloatNormalOutIntXY(x, 5, (float)param->safety.temperature.OT_Chg_Warning / 10, 5, 1);
dis_param->safety.temperature.OT_Chg_Warning = param->safety.temperature.OT_Chg_Warning;
}
// OT Chg Recovery (Offset 3)
if (p || (dis_param->safety.temperature.OT_Chg_Recovery != param->safety.temperature.OT_Chg_Recovery))
{
FloatNormalOutIntXY(x, 6, (float)param->safety.temperature.OT_Chg_Recovery / 10, 5, 1);
dis_param->safety.temperature.OT_Chg_Recovery = param->safety.temperature.OT_Chg_Recovery;
}
// Over Temp Dsg Threshold (Offset 5)
if (p || (dis_param->safety.temperature.OT_Dsg_Threshold != param->safety.temperature.OT_Dsg_Threshold))
{
FloatNormalOutIntXY(x, 8, (float)param->safety.temperature.OT_Dsg_Threshold / 10, 5, 1);
dis_param->safety.temperature.OT_Dsg_Threshold = param->safety.temperature.OT_Dsg_Threshold;
}
// Over Temp Dsg Warning (Offset 5)
if (p || (dis_param->safety.temperature.OT_Dsg_Warning != param->safety.temperature.OT_Dsg_Warning))
{
FloatNormalOutIntXY(x, 9, (float)param->safety.temperature.OT_Dsg_Warning / 10, 5, 1);
dis_param->safety.temperature.OT_Dsg_Warning = param->safety.temperature.OT_Dsg_Warning;
}
// OT Dsg Recovery (Offset 8)
if (p || (dis_param->safety.temperature.OT_Dsg_Recovery != param->safety.temperature.OT_Dsg_Recovery))
{
FloatNormalOutIntXY(x, 10, (float)param->safety.temperature.OT_Dsg_Recovery / 10, 5, 1);
dis_param->safety.temperature.OT_Dsg_Recovery = param->safety.temperature.OT_Dsg_Recovery;
}
// Low temperature
// LT Chg Threshold (Offset 0)
if (p || (dis_param->safety.temperature.LT_Chg_Threshold != param->safety.temperature.LT_Chg_Threshold))
{
FloatNormalOutIntXY(x, 12, (float)param->safety.temperature.LT_Chg_Threshold / 10, 5, 1);
dis_param->safety.temperature.LT_Chg_Threshold = param->safety.temperature.LT_Chg_Threshold;
}
// LT Chg Warning (Offset 2)
if (p || (dis_param->safety.temperature.LT_Chg_Warning != param->safety.temperature.LT_Chg_Warning))
{
FloatNormalOutIntXY(x, 13, (float)param->safety.temperature.LT_Chg_Warning / 10, 5, 1);
dis_param->safety.temperature.LT_Chg_Warning = param->safety.temperature.LT_Chg_Warning;
}
// LT Chg Recovery (Offset 3)
if (p || (dis_param->safety.temperature.LT_Chg_Recovery != param->safety.temperature.LT_Chg_Recovery))
{
FloatNormalOutIntXY(x, 14, (float)param->safety.temperature.LT_Chg_Recovery / 10, 5, 1);
dis_param->safety.temperature.LT_Chg_Recovery = param->safety.temperature.LT_Chg_Recovery;
}
// LT Dsg Threshold (Offset 5)
if (p || (dis_param->safety.temperature.LT_Dsg_Threshold != param->safety.temperature.LT_Dsg_Threshold))
{
FloatNormalOutIntXY(x, 16, (float)param->safety.temperature.LT_Dsg_Threshold / 10, 5, 1);
dis_param->safety.temperature.LT_Dsg_Threshold = param->safety.temperature.LT_Dsg_Threshold;
}
// LT Dsg Warning (Offset 5)
if (p || (dis_param->safety.temperature.LT_Dsg_Warning != param->safety.temperature.LT_Dsg_Warning))
{
FloatNormalOutIntXY(x, 17, (float)param->safety.temperature.LT_Dsg_Warning / 10, 5, 1);
dis_param->safety.temperature.LT_Dsg_Warning = param->safety.temperature.LT_Dsg_Warning;
}
// LT Dsg Recovery (Offset 8)
if (p || (dis_param->safety.temperature.LT_Dsg_Recovery != param->safety.temperature.LT_Dsg_Recovery))
{
FloatNormalOutIntXY(x, 18, (float)param->safety.temperature.LT_Dsg_Recovery / 10, 5, 1);
dis_param->safety.temperature.LT_Dsg_Recovery = param->safety.temperature.LT_Dsg_Recovery;
}
}
void SF1DisplaySVoltage(u8 p)
{
u8 text[20];
PDEVICE_PARAM param = &device_param;
PDEVICE_PARAM dis_param = &dis_device_param;
int x;
x = 73;
// SOV Threshold (Offset 0)
if (p || (dis_param->safety.voltage.SOV_Threshold != param->safety.voltage.SOV_Threshold))
{
sprintf((char *)text, "%4d", param->safety.voltage.SOV_Threshold);
GreenOutXY(x, 4, text);
dis_param->safety.voltage.SOV_Threshold = param->safety.voltage.SOV_Threshold;
}
// SOV Warning (Offset 2)
if (p || (dis_param->safety.voltage.SOV_Warning != param->safety.voltage.SOV_Warning))
{
sprintf((char *)text, "%4d", param->safety.voltage.SOV_Warning);
GreenOutXY(x, 5, text);
dis_param->safety.voltage.SOV_Warning = param->safety.voltage.SOV_Warning;
}
// SOV Recovery (Offset 4)
if (p || (dis_param->safety.voltage.SOV_Recovery != param->safety.voltage.SOV_Recovery))
{
sprintf((char *)text, "%4d", param->safety.voltage.SOV_Recovery);
GreenOutXY(x, 6, text);
dis_param->safety.voltage.SOV_Recovery = param->safety.voltage.SOV_Recovery;
}
// SUV Threshold (Offset 6)
if (p || (dis_param->safety.voltage.SUV_Threshold != param->safety.voltage.SUV_Threshold))
{
sprintf((char *)text, "%4d", param->safety.voltage.SUV_Threshold);
GreenOutXY(x, 8, text);
dis_param->safety.voltage.SUV_Threshold = param->safety.voltage.SUV_Threshold;
}
// SUV Warning (Offset 8)
if (p || (dis_param->safety.voltage.SUV_Warning != param->safety.voltage.SUV_Warning))
{
sprintf((char *)text, "%4d", param->safety.voltage.SUV_Warning);
GreenOutXY(x, 9, text);
dis_param->safety.voltage.SUV_Warning = param->safety.voltage.SUV_Warning;
}
// SUV Recovery (Offset 10)
if (p || (dis_param->safety.voltage.SUV_Recovery != param->safety.voltage.SUV_Recovery))
{
sprintf((char *)text, "%4d", param->safety.voltage.SUV_Recovery);
GreenOutXY(x, 10, text);
dis_param->safety.voltage.SUV_Recovery = param->safety.voltage.SUV_Recovery;
}
}
void SF1DisplayCellVoltageDiff(u8 p)
{
u8 text[20];
PDEVICE_PARAM param = &device_param;
PDEVICE_PARAM dis_param = &dis_device_param;
int x;
x = 73;
// Cell Voltage Diff Threshold (Offset 0)
if (p || (dis_param->safety.cv_diff.Cell_Voltage_Diff_Threshold != param->safety.cv_diff.Cell_Voltage_Diff_Threshold))
{
sprintf((char *)text, "%4d", param->safety.cv_diff.Cell_Voltage_Diff_Threshold);
GreenOutXY(x, 15, text);
dis_param->safety.cv_diff.Cell_Voltage_Diff_Threshold = param->safety.cv_diff.Cell_Voltage_Diff_Threshold;
}
// Cell Voltage Diff Warning (Offset 2)
if (p || (dis_param->safety.cv_diff.Cell_Voltage_Diff_Warning != param->safety.cv_diff.Cell_Voltage_Diff_Warning))
{
sprintf((char *)text, "%4d", param->safety.cv_diff.Cell_Voltage_Diff_Warning);
GreenOutXY(x, 16, text);
dis_param->safety.cv_diff.Cell_Voltage_Diff_Warning = param->safety.cv_diff.Cell_Voltage_Diff_Warning;
}
// Cell Voltage Diff Recovery (Offset 4)
if (p || (dis_param->safety.cv_diff.Cell_Voltage_Diff_Recovery != param->safety.cv_diff.Cell_Voltage_Diff_Recovery))
{
sprintf((char *)text, "%4d", param->safety.cv_diff.Cell_Voltage_Diff_Recovery);
GreenOutXY(x, 17, text);
dis_param->safety.cv_diff.Cell_Voltage_Diff_Recovery = param->safety.cv_diff.Cell_Voltage_Diff_Recovery;
}
}
void SF1DisplayThermistorOpen(u8 p)
{
PDEVICE_PARAM param = &device_param;
PDEVICE_PARAM dis_param = &dis_device_param;
int x;
x = 72;
// Open Thermistor (Offset 0)
if (p || (dis_param->safety.temperature.Open_Thermistor != param->safety.temperature.Open_Thermistor))
{
FloatNormalOutIntXY(x, 19, (float)param->safety.temperature.Open_Thermistor / 10, 5, 1);
dis_param->safety.temperature.Open_Thermistor = param->safety.temperature.Open_Thermistor;
}
// Recovery Thermistor (Offset 2)
if (p || (dis_param->safety.temperature.Recovery_Thermistor != param->safety.temperature.Recovery_Thermistor))
{
FloatNormalOutIntXY(x, 20, (float)param->safety.temperature.Recovery_Thermistor / 10, 5, 1);
dis_param->safety.temperature.Recovery_Thermistor = param->safety.temperature.Recovery_Thermistor;
}
}
void ChgDisplayCellBalCfg(u8 p)
{
u8 text[20];
int x;
x = 19;
// Cell Balance Threshold (Offset 0)
if (p || (dis_device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Threshold != device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Threshold))
{
sprintf((char *)text, "%5d", device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Threshold);
GreenOutXY(x, 17, text);
dis_device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Threshold = device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Threshold;
}
// Cell Balance Window (Offset 2)
if (p || (dis_device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Window != device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Window))
{
sprintf((char *)text, "%5d", device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Window);
GreenOutXY(x, 18, text);
dis_device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Window = device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Window;
}
// Cell Balance Min (Offset 4)
if (p || (dis_device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Min != device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Min))
{
sprintf((char *)text, "%5d", device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Min);
GreenOutXY(x, 19, text);
dis_device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Min = device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Min;
}
x = 21;
// Cell Balance Interval (Offset 6)
if (p || (dis_device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Interval != device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Interval))
{
sprintf((char *)text, "%3d", device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Interval);
GreenOutXY(x, 20, text);
dis_device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Interval = device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Interval;
}
}
void SF1Display(u8 p)
{
SF1DisplayCellVoltage(p);
SF1DisplayTemperature(p);
SF1DisplaySVoltage(p);
SF1DisplayCellVoltageDiff(p);
SF1DisplayThermistorOpen(p);
ChgDisplayCellBalCfg(p);
}
u8 SetSF1_Param(u8 *text, u8 aDevice)
{
u16 size, i, j;
s16 aParam[4];
u8 temp[10];
u8 ret;
u8 cmd;
ret = 0;
size = 0;
while (text[size] != 0x00) size++; /* text의 전체 문자열 size 측정 */
switch (aDevice)
{
case '1': // SF1_VoltageSubClass
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
aParam[0] = StrToInt(temp, j); /* Value */
switch (cmd)
{
case '1': device_param.safety.voltage.COV_Threshold = aParam[0]; break;
case '2': device_param.safety.voltage.COV_Warning = aParam[0]; break;
case '3': device_param.safety.voltage.COV_Recovery = aParam[0]; break;
case '4': device_param.safety.voltage.CUV_Threshold = aParam[0]; break;
case '5': device_param.safety.voltage.CUV_Warning = aParam[0]; break;
case '6': device_param.safety.voltage.CUV_Recovery = aParam[0]; break;
default : return (1);
}
Save_Param();
break;
case '2': // SF1_VoltageSubClass
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
aParam[0] = StrToInt(temp, j); /* Value */
switch (cmd)
{
case '1': device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Threshold = aParam[0]; break;
case '2': device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Window = aParam[0]; break;
case '3': device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Min = aParam[0]; break;
case '4': device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Interval = aParam[0]; break;
default : return (1);
}
Save_Param();
break;
case '3': // SF1_TemperatureSubClass
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
aParam[0] = StrToInt(temp, j); /* Value */
switch (cmd)
{
case '1': device_param.safety.temperature.OT_Chg_Threshold = aParam[0]; break;
case '2': device_param.safety.temperature.OT_Chg_Warning = aParam[0]; break;
case '3': device_param.safety.temperature.OT_Chg_Recovery = aParam[0]; break;
case '4': device_param.safety.temperature.OT_Dsg_Threshold = aParam[0]; break;
case '5': device_param.safety.temperature.OT_Dsg_Warning = aParam[0]; break;
case '6': device_param.safety.temperature.OT_Dsg_Recovery = aParam[0]; break;
case '7': device_param.safety.temperature.LT_Chg_Threshold = aParam[0]; break;
case '8': device_param.safety.temperature.LT_Chg_Warning = aParam[0]; break;
case '9': device_param.safety.temperature.LT_Chg_Recovery = aParam[0]; break;
case 'a': device_param.safety.temperature.LT_Dsg_Threshold = aParam[0]; break;
case 'b': device_param.safety.temperature.LT_Dsg_Warning = aParam[0]; break;
case 'c': device_param.safety.temperature.LT_Dsg_Recovery = aParam[0]; break;
default : return (1);
}
Save_Param();
break;
case '4': // SF1_SVoltageSubClass
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
aParam[0] = StrToInt(temp, j); /* Value */
switch (cmd)
{
case '1': device_param.safety.voltage.SOV_Threshold = aParam[0]; break;
case '2': device_param.safety.voltage.SOV_Warning = aParam[0]; break;
case '3': device_param.safety.voltage.SOV_Recovery = aParam[0]; break;
case '4': device_param.safety.voltage.SUV_Threshold = aParam[0]; break;
case '5': device_param.safety.voltage.SUV_Warning = aParam[0]; break;
case '6': device_param.safety.voltage.SUV_Recovery = aParam[0]; break;
default : return (1);
}
Save_Param();
break;
case '6': // SF1_SocSubClass
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
aParam[0] = StrToInt(temp, j); /* Value */
switch (cmd)
{
case '1': device_param.safety.cv_diff.Cell_Voltage_Diff_Threshold = aParam[0]; break;
case '2': device_param.safety.cv_diff.Cell_Voltage_Diff_Warning = aParam[0]; break;
case '3': device_param.safety.cv_diff.Cell_Voltage_Diff_Recovery = aParam[0]; break;
case '4': device_param.safety.cv_diff.Cell_Voltage_Diff_Time = aParam[0]; break;
default : return (1);
}
Save_Param();
break;
case '7': // SF1_OpenThermistorSubClass
i = 0;
if (size < 2 ) return(1);
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
cmd = temp[0];
j = FIND_CHAR((u8 *)&text[i], temp, size - i, ' ');
i = i + j + 1;
temp[j] = 0x00;
aParam[0] = StrToInt(temp, j); /* Value */
switch (cmd)
{
case '1': device_param.safety.temperature.Open_Thermistor = aParam[0]; break;
case '2': device_param.safety.temperature.Recovery_Thermistor = aParam[0]; break;
default : return (1);
}
Save_Param();
break;
default:
ret = 1;
break;
}
return(ret); /* setting value 정상 */
}
#endif //#ifdef CONSOLE_DEBUG
void SF1_InitData(void)
{
device_param.safety.voltage.COV_Threshold = 3850; // mV
device_param.safety.voltage.COV_Warning = 3750; // mV
device_param.safety.voltage.COV_Recovery = 3580; // mV
device_param.safety.voltage.CUV_Threshold = 2500; // mV
device_param.safety.voltage.CUV_Warning = 2800; // mV
device_param.safety.voltage.CUV_Recovery = 3000; // mV
device_param.safety.voltage.SOV_Threshold = (u16)(3.8 * CellQty * 100); // 10mV 3.8 * 20 = 68.4
device_param.safety.voltage.SOV_Warning = (u16)(3.7 * CellQty * 100); // 10mV 3.7 * 20 = 66.6
device_param.safety.voltage.SOV_Recovery = (u16)(3.6 * CellQty * 100); // 10mV 3.6 * 20 = 64.8
device_param.safety.voltage.SUV_Threshold = (u16)(2.6 * CellQty * 100); // 10mV 2.6 * 20 = 46.8
device_param.safety.voltage.SUV_Warning = (u16)(2.8 * CellQty * 100); // 10mV 2.8 * 20 = 50.4
device_param.safety.voltage.SUV_Recovery = (u16)(3.0 * CellQty * 100); // 10mV 3.0 * 20 = 54.0
device_param.safety.temperature.OT_Chg_Threshold = 600; // 0.1C
device_param.safety.temperature.OT_Chg_Warning = 580; // 0.1C
device_param.safety.temperature.OT_Chg_Recovery = 500; // 0.1C
device_param.safety.temperature.OT_Dsg_Threshold = 700; // 0.1C
device_param.safety.temperature.OT_Dsg_Warning = 680; // 0.1C
device_param.safety.temperature.OT_Dsg_Recovery = 500; // 0.1C
device_param.safety.temperature.LT_Chg_Threshold = -50; // 0.1C
device_param.safety.temperature.LT_Chg_Warning = -30; // 0.1C
device_param.safety.temperature.LT_Chg_Recovery = 0; // 0.1C
device_param.safety.temperature.LT_Dsg_Threshold = -200; // 0.1C
device_param.safety.temperature.LT_Dsg_Warning = -150; // 0.1C
device_param.safety.temperature.LT_Dsg_Recovery = -100; // 0.1C
device_param.safety.temperature.Open_Thermistor = -420; // 0.1C
device_param.safety.temperature.Recovery_Thermistor = -380; // 0.1C
device_param.safety.cv_diff.Cell_Voltage_Diff_Threshold = 1000; // mV
device_param.safety.cv_diff.Cell_Voltage_Diff_Warning = 300; // mV
device_param.safety.cv_diff.Cell_Voltage_Diff_Recovery = 100; // mV
device_param.safety.cv_diff.Cell_Voltage_Diff_Time = 60; // mV
device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Threshold = 3300; // mV
device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Window = 60; // mV
device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Min = 5; // mV
device_param.chg_ctrl.cell_bal_cfg.Cell_Balance_Interval = 5; // Sec
}

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/*****************************************************************************
*
* File : dflash_cfg.h
* Compiler : IAR C 6.30
* Revision : $Revision: 1.0 $
* Date : $Date: 2015 / 03 / 13
* Updated by : $Author: Jongkwang Woo
*
* Support mail : spirit0305@naver.com
*
* Description : Header file for dflash_cfg.c
*
****************************************************************************/
#ifndef _DFLASH_SF1_H_
#define _DFLASH_SF1_H_
#include <stm32f10x.h>
#pragma pack(1)
void SF1_InitData(void);
void SF1Display(u8 p);
s8 Process_DataSF1Set(u8 *text, u16 size);
#endif

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/* Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* High Level description:
* http://www.ti.com/lit/ds/symlink/bq28400.pdf
* Thechnical Reference:
* http://www.ti.com/lit/ug/sluu431/sluu431.pdf
*/
#ifdef CONSOLE_DEBUG
#include "includes.h"
#include "display_status.h"
#include "device_param.h"
#include "asutil.h"
#include "can_comm.h"
#include "delay.h"
#include "io.h"
#include "alarm.h"
void DisplayMsg(u16 x, u16 y, u16 data, u8 bit, u8 *msg)
{
if ((data & BIT(bit)))
RedOutXY(x, y, msg);
else
GreenOutXY(x, y, msg);
}
void DisplayMsg1(u16 x, u16 y, u16 data, u8 bit, u8 *msg)
{
if ((data & BIT(bit)))
YellowOutXY(x, y, msg);
else
GreenOutXY(x, y, msg);
}
void ODisplayBatteryStatus(u8 p)
{
u16 x;
if (p ||(dis_device_status.battery_status.value != device_status.battery_status.value))
{
x = 28;
DisplayMsg(x, 3, device_status.battery_status.value, 15, (u8 *)"ACB"); x += 4;
DisplayMsg(x, 3, device_status.battery_status.value, 14, (u8 *)"TCA"); x += 4;
DisplayMsg(x, 3, device_status.battery_status.value, 13, (u8 *)"TDA"); x += 4;
DisplayMsg(x, 3, device_status.battery_status.value, 12, (u8 *)"AFE"); x += 4;
x += 4;
DisplayMsg(x, 3, device_status.battery_status.value, 10, (u8 *)"ZVC"); x += 4;
DisplayMsg(x, 3, device_status.battery_status.value, 9, (u8 *)"F-C"); x += 4;
DisplayMsg(x, 3, device_status.battery_status.value, 8, (u8 *)"F-D"); x += 4;
x = 28;
DisplayMsg(x, 4, device_status.battery_status.value, 7, (u8 *)"INI"); x += 4;
DisplayMsg(x, 4, device_status.battery_status.value, 6, (u8 *)"MD "); x += 4;
DisplayMsg(x, 4, device_status.battery_status.value, 5, (u8 *)"FC "); x += 4;
DisplayMsg(x, 4, device_status.battery_status.value, 4, (u8 *)"FD "); x += 4;
DisplayMsg(x, 4, device_status.battery_status.value, 3, (u8 *)"RXM"); x += 4;
DisplayMsg(x, 4, device_status.battery_status.value, 2, (u8 *)"ZVC"); x += 4;
DisplayMsg(x, 4, device_status.battery_status.value, 1, (u8 *)"F-C"); x += 4;
DisplayMsg(x, 4, device_status.battery_status.value, 0, (u8 *)"F-D"); x += 4;
dis_device_status.battery_status.value = device_status.battery_status.value;
}
}
void ODisplayWarningStatus(u8 p)
{
u16 x;
if (p ||(dis_device_status.warning.value != device_status.warning.value))
{
x = 28;
x += 4;
x += 4;
x += 4;
DisplayMsg1(x, 6, device_status.warning.value, 12, (u8 *)"L-C"); x += 4;
DisplayMsg1(x, 6, device_status.warning.value, 11, (u8 *)"LTD"); x += 4;
DisplayMsg1(x, 6, device_status.warning.value, 10, (u8 *)"LTC"); x += 4;
DisplayMsg1(x, 6, device_status.warning.value, 9, (u8 *)"HTD"); x += 4;
DisplayMsg1(x, 6, device_status.warning.value, 8, (u8 *)"HTC"); x += 4;
x = 28;
x += 4;
x += 4;
DisplayMsg1(x, 7, device_status.warning.value, 5, (u8 *)"OCD"); x += 4;
DisplayMsg1(x, 7, device_status.warning.value, 4, (u8 *)"OCC"); x += 4;
DisplayMsg1(x, 7, device_status.warning.value, 3, (u8 *)"CUV"); x += 4;
DisplayMsg1(x, 7, device_status.warning.value, 2, (u8 *)"SUV"); x += 4;
DisplayMsg1(x, 7, device_status.warning.value, 1, (u8 *)"COV"); x += 4;
DisplayMsg1(x, 7, device_status.warning.value, 0, (u8 *)"SOV"); x += 4;
dis_device_status.warning.value = device_status.warning.value;
}
}
void ODisplayProtectStatus(u8 p)
{
u16 x;
if (p ||(dis_device_status.protection.value != device_status.protection.value))
{
x = 28;
DisplayMsg(x, 9, device_status.protection.value, 15, (u8 *)"AFE"); x += 4;
x += 4;
DisplayMsg(x, 9, device_status.protection.value, 13, (u8 *)"SC "); x += 4;
x += 4;
DisplayMsg(x, 9, device_status.protection.value, 11, (u8 *)"LTD"); x += 4;
DisplayMsg(x, 9, device_status.protection.value, 10, (u8 *)"LTC"); x += 4;
DisplayMsg(x, 9, device_status.protection.value, 9, (u8 *)"HTD"); x += 4;
DisplayMsg(x, 9, device_status.protection.value, 8, (u8 *)"HTC"); x += 4;
x = 28;
x += 4;
x += 4;
DisplayMsg(x, 10, device_status.protection.value, 5, (u8 *)"OCD"); x += 4;
DisplayMsg(x, 10, device_status.protection.value, 4, (u8 *)"OCC"); x += 4;
DisplayMsg(x, 10, device_status.protection.value, 3, (u8 *)"CUV"); x += 4;
DisplayMsg(x, 10, device_status.protection.value, 2, (u8 *)"SUV"); x += 4;
DisplayMsg(x, 10, device_status.protection.value, 1, (u8 *)"COV"); x += 4;
DisplayMsg(x, 10, device_status.protection.value, 0, (u8 *)"SOV"); x += 4;
dis_device_status.protection.value = device_status.protection.value;
}
}
void ODisplayOperatingStatus(u8 p)
{
u8 text[20];
if (p ||(dis_device_status.op_status != device_status.op_status))
{
switch (device_status.op_status)
{
case 0: // Stand by
GreenOutXY(11, 9, (u8 *)"STAND BY ");
break;
case 1: // Charging
GreenOutXY(11, 9, (u8 *)"CHARGING ");
break;
case 2: // Discharging
GreenOutXY(11, 9, (u8 *)"DISCHARGING");
break;
case 3: // Float
GreenOutXY(11, 9, (u8 *)"FLOAT ");
break;
case 4: // Float
GreenOutXY(11, 9, (u8 *)"WARMING UP ");
break;
default:
sprintf((char *)text, "UNKNOWN(%d)", device_status.op_status);
GreenOutXY(11, 9, text);
break;
}
dis_device_status.op_status = device_status.op_status;
}
}
void ODisplayAlarmStatus(u8 p)
{
if (p ||(dis_device_status.alarm_status != device_status.alarm_status))
{
switch (device_status.alarm_status)
{
case 0: // Normal
GreenOutXY (11, 10, (u8 *)"NORMAL ");
break;
case 1: // Warning
YellowOutXY(11, 10, (u8 *)"WARNING ");
break;
case 2: // Protection
RedOutXY (11, 10, (u8 *)"PROTECTION");
break;
case 3: // WarmingUp
GreenOutXY (11, 10, (u8 *)"WARMING UP");
break;
}
dis_device_status.alarm_status = device_status.alarm_status;
}
}
void ODisplayDeviceLiveStatus(u8 p)
{
uint8_t text[20];
// Device ID
if (p)
{
sprintf((char *)text, "%3d", GetDevAddr());
GreenOutXY(15, 2, text);
}
// Heartbeat
if (p || (dis_device_value.Heartbeat != device_value.Heartbeat))
{
sprintf((char *)text, "%7d", device_value.Heartbeat);
GreenOutXY(11, 3, text);
dis_device_value.Heartbeat = device_value.Heartbeat;
}
}
void ODisplayDeviceValue(u8 p)
{
float aParam;
static int mcount = 0;
if (p|| (mcount == 0))
{
// Battery Voltage
if (p || (dis_device_value.BatVoltage != device_value.BatVoltage))
{
aParam = (float)device_value.BatVoltage / 100;
FloatNormalOutIntXY(12, 5, aParam, 6, 1);
dis_device_value.BatVoltage = device_value.BatVoltage;
}
// Current
if (p || (dis_device_value.Current != device_value.Current))
{
aParam = (float)device_value.Current / 10;
FloatNormalOutIntXY(12, 6, aParam, 6, 1);
dis_device_value.Current = device_value.Current;
}
// RelativeStateOfCharge
if (p || (dis_device_value.RelativeStateOfCharge != device_value.RelativeStateOfCharge))
{
aParam = (float)device_value.RelativeStateOfCharge / 10;
FloatNormalOutIntXY(13, 7, aParam, 5, 1);
dis_device_value.RelativeStateOfCharge = device_value.RelativeStateOfCharge;
}
mcount = 20;
}
mcount--;
}
void ODisplayDeviceStatus(u8 p)
{
u8 text[20];
// OP Status
ODisplayOperatingStatus(p);
ODisplayAlarmStatus(p);
ODisplayBatteryStatus(p);
// Warning Status
if (p || (dis_device_status.warning.value != device_status.warning.value))
{
ODisplayWarningStatus(true);
sprintf((char *)text, "%04X", *(u16 *)&device_status.warning.value);
GreenOutXY(72, 3, text);
dis_device_status.warning.value = device_status.warning.value;
}
// Protection Status
if (p || (dis_device_status.protection.value != device_status.protection.value))
{
ODisplayProtectStatus(true);
sprintf((char *)text, "%04X", *(u16 *)&device_status.protection.value);
GreenOutXY(72, 4, text);
dis_device_status.protection.value = device_status.protection.value;
}
static u8 disSleepMode = 0;
if (p || (disSleepMode != GetSleepMode()))
{
switch (GetSleepMode())
{
case 0: // Normal
GreenOutXY (32, 16, (u8 *)"NORM ");
break;
case 1: // Sleep
RedOutXY (32, 16, (u8 *)"SLEEP");
break;
}
disSleepMode = GetSleepMode();
}
}
void ODisplayCellStatus(u8 p)
{
u16 i, x, y;
float aParam;
static int vcount = 10;
if (p || (vcount == 0))
{
for (i = 0; i < CellQty; i++)
{
x = 5 + ((i / 10) * 11);
y = 12 + (i % 10);
if (p ||(dis_device_value.Cell.voltage[i] != device_value.Cell.voltage[i])
||((dis_device_status.cellbalance.value >> i) & 0x00000001) != ((device_status.cellbalance.value >> i) & 0x00000001))
{
aParam = (float)device_value.Cell.voltage[i] / CELL_DIV_UNIT;
if ((device_status.cellbalance.value >> i) & 0x00000001)
FloatColorOutIntXY(DISPLAY_YELLOW, x, y, aParam, 6, 4);
else
FloatColorOutIntXY(DISPLAY_GREEN, x, y, aParam, 6, 4);
dis_device_value.Cell.voltage[i] = device_value.Cell.voltage[i];
}
}
dis_device_status.cellbalance.value = device_status.cellbalance.value;
vcount = 10;
}
vcount--;
}
void ODisplayAvgValue(u8 p)
{
float aParam;
// Cell Voltage Max, Min, Avg
if (p || (dis_device_value.Cell.avg.Max.value != device_value.Cell.avg.Max.value)) {
aParam = (float)device_value.Cell.avg.Max.value / CELL_DIV_UNIT;
FloatNormalOutIntXY(70, 6 , aParam, 6, 4);
dis_device_value.Cell.avg.Max.value = device_value.Cell.avg.Max.value;
}
if (p || (dis_device_value.Cell.avg.avg != device_value.Cell.avg.avg)) {
aParam = (float)device_value.Cell.avg.avg / CELL_DIV_UNIT;
FloatNormalOutIntXY(70, 7 , aParam, 6, 4);
dis_device_value.Cell.avg.avg = device_value.Cell.avg.avg;
}
if (p || (dis_device_value.Cell.avg.Min.value != device_value.Cell.avg.Min.value)) {
aParam = (float)device_value.Cell.avg.Min.value / CELL_DIV_UNIT;
FloatNormalOutIntXY(70, 8 , aParam, 6, 4);
dis_device_value.Cell.avg.Min.value = device_value.Cell.avg.Min.value;
}
if (p || (dis_device_value.Cell.avg.diff != device_value.Cell.avg.diff)) {
aParam = (float)device_value.Cell.avg.diff / CELL_DIV_UNIT;
FloatNormalOutIntXY(70, 9 , aParam, 6, 4);
dis_device_value.Cell.avg.diff = device_value.Cell.avg.diff;
}
// Temp Max, Min, Avg
if (p || (dis_device_value.Temp.avg.Max.value != device_value.Temp.avg.Max.value))
{
aParam = (float)device_value.Temp.avg.Max.value / 10;
FloatNormalOutIntXY(71, 13, aParam, 5, 1);
dis_device_value.Temp.avg.Max.value = device_value.Temp.avg.Max.value;
}
if (p || (dis_device_value.Temp.avg.avg != device_value.Temp.avg.avg))
{
aParam = (float)device_value.Temp.avg.avg / 10;
FloatNormalOutIntXY(71, 14, aParam, 5, 1);
dis_device_value.Temp.avg.avg = device_value.Temp.avg.avg;
}
if (p || (dis_device_value.Temp.avg.Min.value != device_value.Temp.avg.Min.value))
{
aParam = (float)device_value.Temp.avg.Min.value / 10;
FloatNormalOutIntXY(71, 15, aParam, 5, 1);
dis_device_value.Temp.avg.Min.value = device_value.Temp.avg.Min.value;
}
if (p || (dis_device_value.Temp.avg.diff != device_value.Temp.avg.diff))
{
aParam = (float)device_value.Temp.avg.diff / 10;
FloatNormalOutIntXY(71, 16, aParam, 5, 1);
dis_device_value.Temp.avg.diff = device_value.Temp.avg.diff;
}
}
void ODisplayDevice(u8 p)
{
ODisplayDeviceLiveStatus(p);
ODisplayDeviceStatus(p);
ODisplayDeviceValue(p);
ODisplayCellStatus(p);
ODisplayAvgValue(p);
}
#endif // #ifdef CONSOLE_DEBUG

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/*****************************************************************************
*
* File : device_status.h
* Compiler : IAR C 6.30
* Revision : $Revision: 1.0 $
* Date : $Date: 2015 / 03 / 13
* Updated by : $Author: Jongkwang Woo
*
* Support mail : spirit0305@naver.com
*
* Description : Header file for device_status.c
*
****************************************************************************/
#ifndef _DISPLAY_STATUS_H_
#define _DISPLAY_STATUS_H_
#include <stm32f10x.h>
void ODisplayDevice(u8 p);
#endif

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/**
******************************************************************************
* @file STM32F4xx_IAP/src/flash_if.c
* @author MCD Application Team
* @version V1.0.0
* @date 10-October-2011
* @brief This file provides all the memory related operation functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup STM32F4xx_IAP
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include <stdio.h>
#include <string.h>
#include "flash_if.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
FW_INFO fwinfo;
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @brief Unlocks Flash for write access
* @param None
* @retval None
*/
void FLASH_If_Init(void)
{
FLASH_Unlock();
/* Clear pending flags (if any) */
FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_OPTERR | FLASH_FLAG_WRPRTERR |
FLASH_FLAG_PGERR | FLASH_FLAG_BANK1_EOP | FLASH_FLAG_BANK1_PGERR | FLASH_FLAG_BANK1_WRPRTERR);
}
/**
* @brief Calculate the number of pages
* @param Size: The image size
* @retval The number of pages
*/
uint32_t FLASH_PagesMask(__IO uint32_t Size)
{
uint32_t pagenumber = 0x0;
uint32_t size = Size;
if ((size % PAGE_SIZE) != 0)
{
pagenumber = (size / PAGE_SIZE) + 1;
}
else
{
pagenumber = size / PAGE_SIZE;
}
return pagenumber;
}
/**
* @brief This function does an erase of all user flash area
* @param StartSector: start of user flash area
* @retval 0: user flash area successfully erased
* 1: error occurred
*/
uint32_t FLASH_If_Erase(uint32_t EraseStartAddr, uint32_t uSize)
{
FLASH_Status FLASHStatus = FLASH_COMPLETE;
uint32_t NbrOfPage = 0;
/* init flash */
FLASH_If_Init();
/* Erase the needed pages where the user application will be loaded */
/* Define the number of page to be erased */
NbrOfPage = FLASH_PagesMask(uSize);
/* Erase the FLASH pages */
for (int EraseCounter = 0; (EraseCounter < NbrOfPage) && (FLASHStatus == FLASH_COMPLETE); EraseCounter++)
{
FLASHStatus = FLASH_ErasePage(EraseStartAddr + (PAGE_SIZE * EraseCounter));
}
return (0);
}
/**
* @brief This function writes a data buffer in flash (data are 32-bit aligned).
* @note After writing data buffer, the flash content is checked.
* @param FlashAddress: start address for writing data buffer
* @param Data: pointer on data buffer
* @param DataLength: length of data buffer (unit is 32-bit word)
* @retval 0: Data successfully written to Flash memory
* 1: Error occurred while writing data in Flash memory
* 2: Written Data in flash memory is different from expected one
*/
uint32_t FLASH_If_Write(__IO uint32_t* FlashAddress, uint32_t* Data ,uint32_t DataLength)
{
uint32_t i = 0;
for (i = 0; (i < DataLength) && (*FlashAddress <= (mBMS_FLASH_END_ADDR - 4)); i++)
{
/* Device voltage range supposed to be [2.7V to 3.6V], the operation will
be done by word */
if (FLASH_ProgramWord(*FlashAddress, *(uint32_t*)(Data + i)) == FLASH_COMPLETE)
{
/* Check the written value */
if (*(uint32_t*)*FlashAddress != *(uint32_t*)(Data + i))
{
/* Flash content doesn't match SRAM content */
return (2);
}
/* Increment FLASH destination address */
*FlashAddress += 4;
}
else
{
/* Error occurred while writing data in Flash memory */
return (1);
}
}
return (0);
}
/**
* @brief Disable the write protection of desired pages
* @param None
* @retval None
*/
void FLASH_DisableWriteProtectionPages(void)
{
uint32_t UserMemoryMask = 0;
uint32_t useroptionbyte = 0, WRPR = 0;
uint16_t var1 = OB_IWDG_SW, var2 = OB_STOP_NoRST, var3 = OB_STDBY_NoRST;
FLASH_Status status = FLASH_BUSY;
WRPR = FLASH_GetWriteProtectionOptionByte();
/* Test if user memory is write protected */
if ((WRPR & UserMemoryMask) != UserMemoryMask)
{
useroptionbyte = FLASH_GetUserOptionByte();
UserMemoryMask |= WRPR;
status = FLASH_EraseOptionBytes();
if (UserMemoryMask != 0xFFFFFFFF)
{
status = FLASH_EnableWriteProtection((uint32_t)~UserMemoryMask);
}
/* Test if user Option Bytes are programmed */
if ((useroptionbyte & 0x07) != 0x07)
{
/* Restore user Option Bytes */
if ((useroptionbyte & 0x01) == 0x0)
{
var1 = OB_IWDG_HW;
}
if ((useroptionbyte & 0x02) == 0x0)
{
var2 = OB_STOP_RST;
}
if ((useroptionbyte & 0x04) == 0x0)
{
var3 = OB_STDBY_RST;
}
FLASH_UserOptionByteConfig(var1, var2, var3);
}
if (status == FLASH_COMPLETE)
{
printf("Write Protection disabled...\r\n");
printf("...and a System Reset will be generated to re-load the new option bytes\r\n");
/* Generate System Reset to load the new option byte values */
NVIC_SystemReset();
}
else
{
printf("Error: Flash write unprotection failed...\r\n");
}
}
else
{
printf("Flash memory not write protected\r\n");
}
}
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file STM32F4xx_IAP/inc/flash_if.h
* @author MCD Application Team
* @version V1.0.0
* @date 10-October-2011
* @brief This file provides all the headers of the flash_if functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __FLASH_IF_H
#define __FLASH_IF_H
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u32 AppFileSize;
u8 BootVer[4];
u8 AppVer[4];
u8 FileName[30];
u8 BootUpdate;
u8 AppUpdate;
} FW_INFO;
/* Exported constants --------------------------------------------------------*/
/* Base address of the Flash sectors */
#define FLASH_BASE_ADDRESS 0x8000000
#if defined (STM32F10X_MD) || defined (STM32F10X_MD_VL)
#define PAGE_SIZE (0x400) /* 1 Kbyte */
#define FLASH_SIZE (0x20000) /* 128 KBytes */
#elif defined STM32F10X_CL
#define PAGE_SIZE (0x800) /* 2 Kbytes */
#define FLASH_SIZE (0x40000) /* 256 KBytes */
#elif defined STM32F10X_HD || defined (STM32F10X_HD_VL)
#define PAGE_SIZE (0x800) /* 2 Kbytes */
#define FLASH_SIZE (0x80000) /* 512 KBytes */
#elif defined STM32F10X_XL
#define PAGE_SIZE (0x800) /* 2 Kbytes */
#define FLASH_SIZE (0x100000) /* 1 MByte */
#else
#error "Please select first the STM32 device to be used (in stm32f10x.h)"
#endif
/* Define the address from where user application will be loaded. */
#define mBMS_FLASH_END_ADDR 0x8020000
#define APPLICATION_ADDRESS 0x8003000
#define mBMS_PARAM_BASE_ADDR 0x8002800
#define mBMS_FW_INFO_BASE_ADDR 0x8002C00
#define mBMS_FW_ADDRESS 0x8012000
#define mBMS_FW_END_ADDRESS 0x8020000
#define mBMS_FW_MAX_SIZE mBMS_FW_END_ADDRESS - mBMS_FW_ADDRESS
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void FLASH_If_Init(void);
uint32_t FLASH_If_Erase(uint32_t EraseStartAddr, uint32_t uSize);
uint32_t FLASH_If_Write(__IO uint32_t* FlashAddress, uint32_t* Data, uint32_t DataLength);
void FLASH_DisableWriteProtectionPages(void);
extern FW_INFO fwinfo;
#endif /* __FLASH_IF_H */
/*******************(C)COPYRIGHT 2011 STMicroelectronics *****END OF FILE******/

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/**
******************************************************************************
* File Name : io.c
* Description : This file provides code for the digital input/output.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include <includes.h>
#include "delay.h"
#include "led.h"
#include "device_param.h"
#include "asutil.h"
#include "dflash_sf1.h"
#include "alarm.h"
#include "io.h"
#include "temp.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define IO_TASK_TIME 10 // 50ms TASK
#define RUN_LED_ONOFF_TIME 500 // 500ms
#define DIDCount 2
/*********************** Digital Input Define *********************************/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
u8 device_addr = 0;
TDEVICE_STATUS alarm_device_status;
u8 RunLedFlag = false;
u16 RunLedTick = 0;
u8 RemoteReset = false;
/* Private function prototypes -----------------------------------------------*/
void Led_Process(void);
void dec_led_time(u32 tick);
/* Private function ----------------------------------------------------------*/
void InitDIODevice(void)
{
memset(&alarm_device_status, 0x00, sizeof(TDEVICE_STATUS));
}
u8 GetDevAddrMem(void)
{
return device_param.info.DevAddr;
}
u8 GetDevAddr(void)
{
return device_addr;
}
void SetRemoteReset(void)
{
RemoteReset = true;
}
void App_TaskIO(void)
{
InitDIODevice();
while (DEF_TRUE)
{
device_addr = GetDevAddrMem();
ProcessAlarm();
Led_Process();
if (RemoteReset == true) {
delay_os_ms(100);
Sys_Soft_Reset();
}
delay_os_ms(IO_TASK_TIME);
}
}
void DecIOTaskTick(u32 tick)
{
dec_led_time(tick);
}
void dec_led_time(u32 tick)
{
if (RunLedTick > 0)
{
if (RunLedTick > tick)
RunLedTick -= tick;
else
RunLedTick = 0;
}
}
void Alarm_Led_Process(void)
{
switch (device_status.alarm_status) {
case 0: // Normal
GREEN_LED = ON;
RED_LED = OFF;
break;
case 1: // Warning
GREEN_LED = ON;
RED_LED = ON;
break;
case 2: // Protection
GREEN_LED = OFF;
RED_LED = ON;
break;
case 3: // WarmingUp
GREEN_LED = ON;
RED_LED = OFF;
break;
}
}
void RUN_LED_Process(void)
{
if (RunLedFlag == true) {
if (RunLedTick == 0) {
BD_RUN_LED = ON;
RunLedTick = RUN_LED_ONOFF_TIME;
RunLedFlag = false;
}
} else {
if (RunLedTick == 0) {
BD_RUN_LED = OFF;
RunLedTick = RUN_LED_ONOFF_TIME;
RunLedFlag = true;
}
}
}
void Led_Process(void)
{
if (GetSleepMode() == false) {
RUN_LED_Process();
Alarm_Led_Process();
} else {
BD_RUN_LED = OFF;
GREEN_LED = OFF;
RED_LED = OFF;
}
}
void MP2642_Enable_Ctrl(uint8_t ch, uint8_t enable)
{
switch (ch) {
case 0: MP2642_ENABLE_01 = enable; break;
case 1: MP2642_ENABLE_02 = enable; break;
case 2: MP2642_ENABLE_03 = enable; break;
case 3: MP2642_ENABLE_04 = enable; break;
case 4: MP2642_ENABLE_05 = enable; break;
case 5: MP2642_ENABLE_06 = enable; break;
case 6: MP2642_ENABLE_07 = enable; break;
case 7: MP2642_ENABLE_08 = enable; break;
case 8: MP2642_ENABLE_09 = enable; break;
case 9: MP2642_ENABLE_10 = enable; break;
case 10: MP2642_ENABLE_11 = enable; break;
case 11: MP2642_ENABLE_12 = enable; break;
case 12: MP2642_ENABLE_13 = enable; break;
case 13: MP2642_ENABLE_14 = enable; break;
case 14: MP2642_ENABLE_15 = enable; break;
case 15: MP2642_ENABLE_16 = enable; break;
case 16: MP2642_ENABLE_17 = enable; break;
case 17: MP2642_ENABLE_18 = enable; break;
case 18: MP2642_ENABLE_19 = enable; break;
case 19: MP2642_ENABLE_20 = enable; break;
default: break;
}
}
void MP2642_EnaDis_All(uint8_t enable)
{
MP2642_ENABLE_01 = enable;
MP2642_ENABLE_02 = enable;
MP2642_ENABLE_03 = enable;
MP2642_ENABLE_04 = enable;
MP2642_ENABLE_05 = enable;
MP2642_ENABLE_06 = enable;
MP2642_ENABLE_07 = enable;
MP2642_ENABLE_08 = enable;
MP2642_ENABLE_09 = enable;
MP2642_ENABLE_10 = enable;
MP2642_ENABLE_11 = enable;
MP2642_ENABLE_12 = enable;
MP2642_ENABLE_13 = enable;
MP2642_ENABLE_14 = enable;
MP2642_ENABLE_15 = enable;
MP2642_ENABLE_16 = enable;
MP2642_ENABLE_17 = enable;
MP2642_ENABLE_18 = enable;
MP2642_ENABLE_19 = enable;
MP2642_ENABLE_20 = enable;
}

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/*****************************************************************************
*
* MSO Corporation
*
* File : io.h
* Compiler : IAR C 5.30C Kickstart
* Revision : $Revision: 1.0 $
* Date : $Date: 2012 / 4 / 30
* Updated by : $Author: Jongkwang Woo
*
* Support mail : spirit0305@naver.com
*
* Description : Header file for io.c
*
****************************************************************************/
#ifndef _IO_H_
#define _IO_H_
#include <stm32f10x.h>
void App_TaskIO(void);
void DecIOTaskTick(u32 tick);
u8 GetDevAddr(void);
void SetRemoteReset(void);
void MP2642_Enable_Ctrl(uint8_t ch, uint8_t enable);
void MP2642_EnaDis_All(uint8_t enable);
#endif

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/************************************
REVISION HISTORY
$Revision: 1200 $
$Date: 2016-3-9
Copyright (c) 2015, Linear Technology Corp.(LTC)
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of Linear Technology Corp.
The Linear Technology Linduino is not affiliated with the official Arduino team.
However, the Linduino is only possible because of the Arduino team's commitment
to the open-source community. Please, visit http://www.arduino.cc and
http://store.arduino.cc , and consider a purchase that will help fund their
ongoing work.
Copyright 2015 Linear Technology Corp. (LTC)
***********************************************************/
/*! @file
@ingroup ltc68111
Header for ltc6811-1 Multicell Battery Monitor
*/
#ifndef LTC68111_H
#define LTC68111_H
#ifndef LTC6811_CS
#define LTC6811_CS QUIKEVAL_CS
#endif
#define MD_422HZ_1KHZ 0
#define MD_27KHZ_14KHZ 1
#define MD_7KHZ_3KHZ 2
#define MD_26HZ_2KHZ 3
#define ADC_OPT_ENABLED 1
#define ADC_OPT_DISABLED 0
#define CELL_CH_ALL 0
#define CELL_CH_1and7 1
#define CELL_CH_2and8 2
#define CELL_CH_3and9 3
#define CELL_CH_4and10 4
#define CELL_CH_5and11 5
#define CELL_CH_6and12 6
#define SELFTEST_1 1
#define SELFTEST_2 2
#define AUX_CH_ALL 0
#define AUX_CH_GPIO1 1
#define AUX_CH_GPIO2 2
#define AUX_CH_GPIO3 3
#define AUX_CH_GPIO4 4
#define AUX_CH_GPIO5 5
#define AUX_CH_VREF2 6
#define STAT_CH_ALL 0
#define STAT_CH_SOC 1
#define STAT_CH_ITEMP 2
#define STAT_CH_VREGA 3
#define STAT_CH_VREGD 4
#define DCP_DISABLED 0
#define DCP_ENABLED 1
#define PULL_UP_CURRENT 1
#define PULL_DOWN_CURRENT 0
#define CELL_CHANNELS 12
#define AUX_CHANNELS 6
#define STAT_CHANNELS 4
#define CELL 1
#define AUX 2
#define STAT 3
/*! Starts the Mux Decoder diagnostic self test
Running this command will start the Mux Decoder Diagnostic Self Test
This test takes roughly 1mS to complete. The MUXFAIL bit will be updated,
the bit will be set to 1 for a failure and 0 if the test has been passed.
*/
void ltc6811_diagn();
//! Sends the poll adc command
//! @returns 1 byte read back after a pladc command. If the byte is not 0xFF ADC conversion has completed
uint8_t ltc6811_pladc();
//! This function will block operation until the ADC has finished it's conversion
//! @returns the approximate time it took for the ADC function to complete.
uint32_t ltc6811_pollAdc();
/*! Starts cell voltage conversion
Starts ADC conversions of the ltc6811 Cpin inputs.
The type of ADC conversion executed can be changed by setting the following parameters:
|Variable|Function |
|--------|----------------------------------------------|
| MD | Determines the filter corner of the ADC |
| CH | Determines which cell channels are converted |
| DCP | Determines if Discharge is Permitted |
| ST | Determines which Self Test is executed |
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|ADCV: | 0 | 0 | 0 | 0 | 0 | 0 | 1 | MD[1] | MD[2] | 1 | 1 | DCP | 0 | CH[2] | CH[1] | CH[0] |
*/
void ltc6811_adcv(uint8_t MD, //!< ADC Conversion Mode
uint8_t DCP, //!< Controls if Discharge is permitted during conversion
uint8_t CH //!< Sets which Cell channels are converted
);
/*! Starts cell voltage and GPIO 1&2 conversion
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|ADCVAX: | 0 | 0 | 0 | 0 | 0 | 1 | 0 | MD[1] | MD[2] | 1 | 1 | DCP | 1 | 1 | 1 | 1 |
*/
void ltc6811_adcvax(
uint8_t MD, //!< ADC Conversion Mode
uint8_t DCP //!< Controls if Discharge is permitted during conversion
);
/*! Starts cell voltage self test conversion
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|CVST: | 0 | 0 | 0 | 0 | 0 | 0 | 1 | MD[1] | MD[2] | ST[1] | ST[0] | 0 | 0 | 1 | 1 | 1 |
*/
void ltc6811_cvst(
uint8_t MD, //!< ADC Conversion Mode
uint8_t ST //!< Self Test Mode
);
/*! Starts cell voltage and SOC conversion
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|ADCVSC: | 0 | 0 | 0 | 0 | 0 | 1 | 0 | MD[1] | MD[2] | 1 | 1 | DCP | 0 | 1 | 1 | 1 |
*/
void ltc6811_adcvsc(
uint8_t MD, //!< ADC Conversion Mode
uint8_t DCP //!< Controls if Discharge is permitted during conversion
);
/*! Starts cell voltage overlap conversion
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|ADCV: | 0 | 0 | 0 | 0 | 0 | 0 | 1 | MD[1] | MD[2] | 0 | 0 | DCP | 0 | 0 | 0 | 1 |
*/
void ltc6811_adol(
uint8_t MD, //!< ADC Conversion Mode
uint8_t DCP //!< Discharge permitted during conversion
);
/*! Start an open wire Conversion
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|ADOW: | 0 | 0 | 0 | 0 | 0 | 0 | 1 | MD[1] | MD[2] | PUP | 1 | DCP | 1 | CH[2] | CH[1] | CH[0] |
*/
void ltc6811_adow(
uint8_t MD, //!< ADC Conversion Mode
uint8_t PUP //!< Controls if Discharge is permitted during conversion
);
/*! Start GPIO and Vref2 Conversion
The type of ADC conversion executed can be changed by passing the following variables to the conversion functions:
|Variable|Function |
|--------|----------------------------------------------|
| MD | Determines the filter corner of the ADC |
| CHG | Determines which GPIO channels are converted |
| ST | Determines which Self Test is executed |
Starts an ADC conversions of the ltc6811 GPIO inputs.
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|ADAX: | 0 | 0 | 0 | 0 | 0 | 1 | 0 | MD[1] | MD[2] | 1 | 1 | 0 | 0 | CHG[2]| CHG[1]| CHG[0]|
*/
void ltc6811_adax(
uint8_t MD, //!< ADC Conversion Mode
uint8_t CHG //!< Sets which GPIO channels are converted
);
/*! Start an GPIO Redundancy self test
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|ADAXD: | 0 | 0 | 0 | 0 | 0 | 1 | 0 | MD[1] | MD[2] | 0 | 0 | 0 | 0 | CHG[2]| CHG[1]| CHG[0]|
*/
void ltc6811_adaxd(
uint8_t MD, //!< ADC Conversion Mode
uint8_t CHG //!< Sets which GPIO channels are converted
);
/*! Start an Auxiliary Register Self Test Conversion
Starts an ADC conversions for testing the Auxiliary register memory.
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|AXST: | 0 | 0 | 0 | 0 | 0 | 1 | 0 | MD[1] | MD[2] | ST[1] | ST[0] | 0 | 0 | 1 | 1 | 1 |
*/
void ltc6811_axst(
uint8_t MD, //!< ADC Conversion Mode
uint8_t ST //!< Sets if self test 1 or 2 is run
);
/*! Start a Status ADC Conversion
Starts an ADC conversions of the ltc6811 status inputs.
The type of ADC conversion executed can be changed by passing the following variables to the conversion functions:
|Variable|Function |
|--------|-----------------------------------------------|
| MD | Determines the filter corner of the ADC |
| CHST | Determines which status channels are converted|
| ST | Determines which Self Test is executed |
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|--------|--------|--------|
|ADSTAT: | 0 | 0 | 0 | 0 | 0 | 1 | 0 | MD[1] | MD[2] | 1 | 1 | 0 | 1 | CHST[2]| CHST[1]| CHST[0]|
*/
void ltc6811_adstat(
uint8_t MD, //!< ADC Conversion Mode
uint8_t CHST //!< Sets which Stat channels are converted
);
/*! Start a Status register redundancy test Conversion
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|--------|--------|--------|
|ASTATD: | 0 | 0 | 0 | 0 | 0 | 1 | 0 | MD[1] | MD[2] | 0 | 0 | 0 | 1 | CHST[2]| CHST[1]| CHST[0]|
*/
void ltc6811_adstatd(
uint8_t MD, //!< ADC Mode
uint8_t CHST //!< Sets which Status channels are converted
);
/*! Start a Status Register Self Test Conversion
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|--------|--------|--------|
|STATST: | 0 | 0 | 0 | 0 | 0 | 1 | 0 | MD[1] | MD[2] | ST[1] | ST[0] | 0 | 1 | 1 | 1 | 1 |
*/
void ltc6811_statst(
uint8_t MD, //!< ADC Conversion Mode
uint8_t ST //!< Sets if self test 1 or 2 is run
);
/*! Reads and parses the ltc6811 cell voltage registers.
The function is used to read the cell codes of the ltc6811.
This function will send the requested read commands parse the data
and store the cell voltages in cell_codes variable.
uint8_t reg; This controls which cell voltage register is read back.
0: Read back all Cell registers
1: Read back cell group A
2: Read back cell group B
3: Read back cell group C
4: Read back cell group D
uint8_t total_ic; This is the number of ICs in the daisy chain(-1 only)
uint16_t cell_codes[]; An array of the parsed cell codes from lowest to highest. The cell codes will
be stored in the cell_codes[] array in the following format:
| cell_codes[0][0]| cell_codes[0][1] | cell_codes[0][2]| ..... | cell_codes[0][11]| cell_codes[1][0] | cell_codes[1][1]| ..... |
|------------------|------------------|------------------|--------------|-------------------|-------------------|-----------------|----------|
|IC1 Cell 1 |IC1 Cell 2 |IC1 Cell 3 | ..... | IC1 Cell 12 |IC2 Cell 1 |IC2 Cell 2 | ..... |
@return int8_t, PEC Status.
0: No PEC error detected
-1: PEC error detected, retry read
*/
uint8_t ltc6811_rdcv(uint8_t reg, //!< controls which cell voltage register is read back.
uint8_t total_ic, //!< the number of ICs in the daisy chain(-1 only)
uint16_t cell_codes[][CELL_CHANNELS] //!< array of the parsed cell codes from lowest to highest.
);
/*! Read the raw data from the ltc6811 cell voltage register
The function reads a single cell voltage register and stores the read data
in the *data point as a byte array. This function is rarely used outside of
the ltc6811_rdcv() command.
@param[in] uint8_t reg; This controls which cell voltage register is read back.
1: Read back cell group A
2: Read back cell group B
3: Read back cell group C
4: Read back cell group D
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|RDCVA: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
|RDCVB: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
|RDCVC: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
|RDCVD: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
*/
void ltc6811_rdcv_reg(uint8_t reg, //!< Controls which cell voltage register is read back.
uint8_t nIC, //!< The number of ICs in the daisy chain
uint8_t *data //!< An array of the unparsed cell codes
);
/*! Reads and parses the ltc6811 auxiliary registers.
The function is used to read the parsed GPIO codes of the ltc6811. This function will send the requested
read commands parse the data and store the gpio voltages in aux_codes variable
uint16_t aux_codes[][6]; A two dimensional array of the gpio voltage codes. The GPIO codes will
be stored in the aux_codes[][6] array in the following format:
| aux_codes[0][0]| aux_codes[0][1] | aux_codes[0][2]| aux_codes[0][3]| aux_codes[0][4]| aux_codes[0][5]| aux_codes[1][0] |aux_codes[1][1]| ..... |
|-----------------|-----------------|-----------------|-----------------|-----------------|-----------------|-----------------|---------------|-----------|
|IC1 GPIO1 |IC1 GPIO2 |IC1 GPIO3 |IC1 GPIO4 |IC1 GPIO5 |IC1 Vref2 |IC2 GPIO1 |IC2 GPIO2 | ..... |
@return int8_t, PEC Status
0: No PEC error detected
-1: PEC error detected, retry read
*/
int8_t ltc6811_rdaux(uint8_t reg, //!< controls which GPIO voltage register is read back
uint8_t nIC, //!< the number of ICs in the daisy chain
uint16_t aux_codes[][AUX_CHANNELS] //!< A two dimensional array of the parsed gpio voltage codes
);
/*! Read the raw data from the ltc6811 auxiliary register
The function reads a single GPIO voltage register and stores thre read data
in the *data point as a byte array. This function is rarely used outside of
the ltc6811_rdaux() command.
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|RDAUXA: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
|RDAUXB: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
*/
void ltc6811_rdaux_reg(uint8_t reg, //!< controls which GPIO voltage register is read back
uint8_t nIC, //!< the number of ICs in the daisy chain
uint8_t *data //!< An array of the unparsed aux codes
);
/*! Read the raw data from the ltc6811 stat register
The function reads a single GPIO voltage register and stores thre read data
in the *data point as a byte array. This function is rarely used outside of
the ltc6811_rdstat() command.
@param[in] uint8_t reg; This controls which GPIO voltage register is read back.
1: Read back stat group A
2: Read back stat group B
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|RDstatA: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
|RDstatB: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |
*/
void ltc6811_rdstat_reg(uint8_t reg, //!< Determines which GPIO voltage register is read back
uint8_t total_ic, //!< the number of ICs in the daisy chain
uint8_t *data //!< Array of the unparsed statiliary codes
);
/*! Reads and parses the ltc6811 stat registers.
The function is used to read the parsed status codes of the ltc6811. This function will send the requested
read commands parse the data and store the status voltages in stat_codes variable
@param[in] uint8_t reg; This controls which GPIO voltage register is read back.
0: Read back all stat registers
1: Read back stat group A
2: Read back stat group B
uint16_t stat_codes[][6]; A two dimensional array of the gpio voltage codes. The GPIO codes will
be stored in the stat_codes[][6] array in the following format:
| stat_codes[0][0]| stat_codes[0][1] | stat_codes[0][2]| stat_codes[0][3]| stat_codes[1][0] |stat_codes[1][1]| ..... |
|------------------|------------------|------------------|------------------|------------------|----------------|-----------|
|IC1 SOC |IC1 ITMP |IC1 VregA |IC1 VregD |IC2 SOC |IC2 ITMP | ..... |
@return int8_t, PEC Status
0: No PEC error detected
-1: PEC error detected, retry read
*/
int8_t ltc6811_rdstat(uint8_t reg, //!< Determines which GPIO voltage register is read back.
uint8_t total_ic,//!< the number of ICs in the system
uint16_t stat_codes[][4],//!< A two dimensional array of the stat voltage codes.
uint8_t flags[][3], //!< byte array that contains the uv/ov flag data
uint8_t mux_fail[][1], //!< Mux self test status flag
uint8_t thsd[][1] //!< Thermal shutdown status
);
/*! Clears the ltc6811 cell voltage registers
The command clears the cell voltage registers and initializes
all values to 1. The register will read back hexadecimal 0xFF
after the command is sent.
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|CLRCELL: | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
*/
void ltc6811_clrcell();
/*! Clears the ltc6811 Auxiliary registers
The command clears the Auxiliary registers and initializes
all values to 1. The register will read back hexadecimal 0xFF
after the command is sent.
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|CLRAUX: | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |
*/
void ltc6811_clraux();
/*! Clears the ltc6811 Stat registers
The command clears the Stat registers and initializes
all values to 1. The register will read back hexadecimal 0xFF
after the command is sent.
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|CLRSTAT: | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
*/
void ltc6811_clrstat();
/*! Clears the ltc6811 Sctrl registers
The command clears the Sctrl registers and initializes
all values to 0. The register will read back hexadecimal 0x00
after the command is sent.
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|CLRSCTRL: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
*/
void ltc6811_clrsctrl();
/*! Write the ltc6811 configuration register
This command will write the configuration registers of the ltc6811-1s
connected in a daisy chain stack. The configuration is written in descending
order so the last device's configuration is written first.
uint8_t config[][6] is a two dimensional array of the configuration data that will be written, the array should contain the 6 bytes for each
IC in the daisy chain. The lowest IC in the daisy chain should be the first 6 byte block in the array. The array should
have the following format:
| config[0][0]| config[0][1] | config[0][2]| config[0][3]| config[0][4]| config[0][5]| config[1][0] | config[1][1]| config[1][2]| ..... |
|--------------|--------------|--------------|--------------|--------------|--------------|--------------|--------------|--------------|-----------|
|IC1 CFGR0 |IC1 CFGR1 |IC1 CFGR2 |IC1 CFGR3 |IC1 CFGR4 |IC1 CFGR5 |IC2 CFGR0 |IC2 CFGR1 | IC2 CFGR2 | ..... |
The function will calculate the needed PEC codes for the write data
and then transmit data to the ICs on a daisy chain.
Command Code:
-------------
| | CMD[0] | CMD[1] |
|---------------|---------------------------------------------------------------|---------------------------------------------------------------|
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|WRCFG: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
*/
void ltc6811_wrcfg(uint8_t nIC, //!< The number of ICs being written
uint8_t config[][6] //!< a two dimensional array of the configuration data that will be written
);
/*! Reads configuration registers of a ltc6811 daisy chain
uint8_t r_config[][8] is a two dimensional array that the function stores the read configuration data. The configuration data for each IC
is stored in blocks of 8 bytes with the configuration data of the lowest IC on the stack in the first 8 bytes
block of the array, the second IC in the second 8 byte etc. Below is an table illustrating the array organization:
|r_config[0][0]|r_config[0][1]|r_config[0][2]|r_config[0][3]|r_config[0][4]|r_config[0][5]|r_config[0][6] |r_config[0][7] |r_config[1][0]|r_config[1][1]| ..... |
|--------------|--------------|--------------|--------------|--------------|--------------|----------------|---------------|--------------|--------------|-----------|
|IC1 CFGR0 |IC1 CFGR1 |IC1 CFGR2 |IC1 CFGR3 |IC1 CFGR4 |IC1 CFGR5 |IC1 PEC High |IC1 PEC Low |IC2 CFGR0 |IC2 CFGR1 | ..... |
@return int8_t, PEC Status.
0: Data read back has matching PEC
-1: Data read back has incorrect PEC
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|RDCFG: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
*/
int8_t ltc6811_rdcfg(uint8_t nIC, //!< number of ICs in the daisy chain
uint8_t r_config[][8] //!< a two dimensional array that the function stores the read configuration data
);
/*! Write the ltc6811 PWM register
This command will write the pwm registers of the ltc6811-1s
connected in a daisy chain stack. The pwm is written in descending
order so the last device's pwm is written first.
uint8_t pwm[][6] is a two dimensional array of the pwm data that will be written, the array should contain the 6 bytes for each
IC in the daisy chain. The lowest IC in the daisy chain should be the first 6 byte block in the array. The array should
have the following format:
| pwm[0][0]| pwm[0][1] | pwm[0][2]| pwm[0][3]| pwm[0][4]| pwm[0][5]| pwm[1][0] | pwm[1][1]| pwm[1][2]| ..... |
|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|-----------|
|IC1 pwm0 |IC1 pwm1 |IC1 pwm2 |IC1 pwm3 |IC1 pwm4 |IC1 pwm5 |IC2 pwm0 |IC2 pwm1 | IC2 pwm2 | ..... |
The function will calculate the needed PEC codes for the write data
and then transmit data to the ICs on a daisy chain.
Command Code:
-------------
| | CMD[0] | CMD[1] |
|---------------|---------------------------------------------------------------|---------------------------------------------------------------|
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|WRPWM: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
*/
void ltc6811_wrpwm(uint8_t nIC, //!< number of ICs in the daisy chain
uint8_t pwmReg,
uint8_t pwm[][6]
);
/*! Reads pwm registers of a ltc6811 daisy chain
uint8_t r_pwm[][8] is a two dimensional array that the function stores the read pwm data. The pwm data for each IC
is stored in blocks of 8 bytes with the pwm data of the lowest IC on the stack in the first 8 bytes
block of the array, the second IC in the second 8 byte etc. Below is an table illustrating the array organization:
|r_pwm[0][0]|r_pwm[0][1]|r_pwm[0][2]|r_pwm[0][3]|r_pwm[0][4]|r_pwm[0][5]|r_pwm[0][6] |r_pwm[0][7] |r_pwm[1][0]|r_pwm[1][1]| ..... |
|-----------|-----------|-----------|-----------|-----------|-----------|-------------|------------|-----------|-----------|-----------|
|IC1 pwm0 |IC1 pwm1 |IC1 pwm2 |IC1 pwm3 |IC1 pwm4 |IC1 pwm5 |IC1 PEC High |IC1 PEC Low |IC2 CFGR0 |IC2 CFGR1 | ..... |
@return int8_t, PEC Status.
0: Data read back has matching PEC
-1: Data read back has incorrect PEC
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|RDPWM: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
*/
int8_t ltc6811_rdpwm(uint8_t nIC, //!< number of ICs in the daisy chain
uint8_t pwmReg,
uint8_t r_pwm[][8] //!< a two dimensional array that the function stores the read pwm data
);
/*! Write the ltc6811 Sctrl register
This command will write the pwm registers of the ltc6811-1s
connected in a daisy chain stack. The pwm is written in descending
order so the last device's pwm is written first.
The function will calculate the needed PEC codes for the write data
and then transmit data to the ICs on a daisy chain.
Command Code:
-------------
| | CMD[0] | CMD[1] |
|---------------|---------------------------------------------------------------|---------------------------------------------------------------|
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|WRSCTRL: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
*/
void ltc6811_wrsctrl(uint8_t nIC, //!< number of ICs in the daisy chain
uint8_t sctrl_reg,
uint8_t sctrl[][6]
);
/*! Reads sctrl registers of a ltc6811 daisy chain
uint8_t r_sctrl[][8] is a two dimensional array that the function stores the read pwm data. The sctrl data for each IC
is stored in blocks of 8 bytes with the pwm data of the lowest IC on the stack in the first 8 bytes
block of the array, the second IC in the second 8 byte etc. Below is an table illustrating the array organization:
@return int8_t, PEC Status.
0: Data read back has matching PEC
-1: Data read back has incorrect PEC
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|rdsctrl: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
*/
int8_t ltc6811_rdsctrl(uint8_t nIC, //!< number of ICs in the daisy chain
uint8_t sctrl_reg,
uint8_t r_sctrl[][8] //!< a two dimensional array that the function stores the read pwm data
);
/*! Start Sctrl data communication
This command will start the sctrl pulse communication over the spins
Command Code:
-------------
| | CMD[0] | CMD[1] |
|---------------|---------------------------------------------------------------|---------------------------------------------------------------|
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|stsctrl: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
*/
void ltc6811_stsctrl();
/*! Write the ltc6811 COMM register
This command will write the comm registers of the ltc6811-1s
connected in a daisy chain stack. The comm is written in descending
order so the last device's configuration is written first.
uint8_t comm[][6] is a two dimensional array of the configuration data that will be written, the array should contain the 6 bytes for each
IC in the daisy chain. The lowest IC in the daisy chain should be the first 6 byte block in the array. The array should
have the following format:
| COMM[0][0]| COMM[0][1] | COMM[0][2]| COMM[0][3]| COMM[0][4]| COMM[0][5]| COMM[1][0] | COMM[1][1]| COMM[1][2]| ..... |
|------------|------------|------------|------------|------------|------------|------------|------------|------------|-----------|
|IC1 COMM0 |IC1 COMM1 |IC1 COMM2 |IC1 COMM3 |IC1 COMM4 |IC1 COMM5 |IC2 COMM0 |IC2 COMM1 | IC2 COMM2 | ..... |
The function will calculate the needed PEC codes for the write data
and then transmit data to the ICs on a daisy chain.
Command Code:
-------------
| | CMD[0] | CMD[1] |
|---------------|---------------------------------------------------------------|---------------------------------------------------------------|
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|WRCOMM: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
*/
void ltc6811_wrcomm(uint8_t total_ic, //!< Number of ICs in the daisy chain
uint8_t comm[][6] //!< A two dimensional array of the comm data that will be written
);
/*! Reads comm registers of a ltc6811 daisy chain
uint8_t r_comm[][8] is a two dimensional array that the function stores the read comm data. The comm data for each IC
is stored in blocks of 8 bytes with the comm data of the lowest IC on the stack in the first 8 bytes
block of the array, the second IC in the second 8 byte etc. Below is an table illustrating the array organization:
|r_comm[0][0]|r_comm[0][1]|r_comm[0][2]|r_comm[0][3]|r_comm[0][4]|r_comm[0][5]|r_comm[0][6] |r_comm[0][7] |r_comm[1][0]|r_comm[1][1]| ..... |
|------------|------------|------------|------------|------------|------------|-------------|-------------|------------|------------|-----------|
|IC1 comm0 |IC1 comm1 |IC1 comm2 |IC1 comm3 |IC1 comm4 |IC1 comm5 |IC1 PEC High |IC1 PEC Low |IC2 CFGR0 |IC2 CFGR1 | ..... |
@return int8_t, PEC Status.
0: Data read back has matching PEC
-1: Data read back has incorrect PEC
Command Code:
-------------
|CMD[0:1] | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---------------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|-------|
|RDCCOMM: | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
*/
int8_t ltc6811_rdcomm(uint8_t total_ic, //!< number of ICs in the daisy chain
uint8_t r_comm[][8] //!< Two dimensional array that the function stores the read comm data.
);
/*! issues a stcomm command and clocks data out of the COMM register */
void ltc6811_stcomm();
/*! Wake isoSPI up from idle state */
void wakeup_idle();
/*! Wake the ltc6811 from the sleep state */
void wakeup_sleep();
/*! calculates and returns the CRC15
@returns The calculated pec15 as an unsigned int
*/
uint16_t pec15_calc(uint8_t len, //!< the length of the data array being passed to the function
uint8_t *data //!< the array of data that the PEC will be generated from
);
/*! @returns returns the register data pattern for a given ADC MD and Self test */
uint16_t ltc6811_st_lookup(
uint8_t MD, //!< ADC Conversion Mode
uint8_t ST //!< Self test number
);
/*! Writes an array of bytes out of the SPI port*/
void spi_write_array(uint8_t length, //!< length of the data array being written on the SPI port
uint8_t *data); //!< the data array to be written on the SPI port
/*! Writes and read a set number of bytes using the SPI port. */
void spi_write_read(uint8_t *TxData, //!< array of data to be written on the SPI port
uint8_t TXlen, //!< tx_len length of the tx_data array
uint8_t *rx_data, //!< rx_data array that read data will be written too.
uint8_t RXlen); //!< number of bytes to be read from the SPI port.
const uint16_t crc15Table[256] PROGMEM = {0x0,0xc599, 0xceab, 0xb32, 0xd8cf, 0x1d56, 0x1664, 0xd3fd, 0xf407, 0x319e, 0x3aac, //!<precomputed CRC15 Table
0xff35, 0x2cc8, 0xe951, 0xe263, 0x27fa, 0xad97, 0x680e, 0x633c, 0xa6a5, 0x7558, 0xb0c1,
0xbbf3, 0x7e6a, 0x5990, 0x9c09, 0x973b, 0x52a2, 0x815f, 0x44c6, 0x4ff4, 0x8a6d, 0x5b2e,
0x9eb7, 0x9585, 0x501c, 0x83e1, 0x4678, 0x4d4a, 0x88d3, 0xaf29, 0x6ab0, 0x6182, 0xa41b,
0x77e6, 0xb27f, 0xb94d, 0x7cd4, 0xf6b9, 0x3320, 0x3812, 0xfd8b, 0x2e76, 0xebef, 0xe0dd,
0x2544, 0x2be, 0xc727, 0xcc15, 0x98c, 0xda71, 0x1fe8, 0x14da, 0xd143, 0xf3c5, 0x365c,
0x3d6e, 0xf8f7,0x2b0a, 0xee93, 0xe5a1, 0x2038, 0x7c2, 0xc25b, 0xc969, 0xcf0, 0xdf0d,
0x1a94, 0x11a6, 0xd43f, 0x5e52, 0x9bcb, 0x90f9, 0x5560, 0x869d, 0x4304, 0x4836, 0x8daf,
0xaa55, 0x6fcc, 0x64fe, 0xa167, 0x729a, 0xb703, 0xbc31, 0x79a8, 0xa8eb, 0x6d72, 0x6640,
0xa3d9, 0x7024, 0xb5bd, 0xbe8f, 0x7b16, 0x5cec, 0x9975, 0x9247, 0x57de, 0x8423, 0x41ba,
0x4a88, 0x8f11, 0x57c, 0xc0e5, 0xcbd7, 0xe4e, 0xddb3, 0x182a, 0x1318, 0xd681, 0xf17b,
0x34e2, 0x3fd0, 0xfa49, 0x29b4, 0xec2d, 0xe71f, 0x2286, 0xa213, 0x678a, 0x6cb8, 0xa921,
0x7adc, 0xbf45, 0xb477, 0x71ee, 0x5614, 0x938d, 0x98bf, 0x5d26, 0x8edb, 0x4b42, 0x4070,
0x85e9, 0xf84, 0xca1d, 0xc12f, 0x4b6, 0xd74b, 0x12d2, 0x19e0, 0xdc79, 0xfb83, 0x3e1a, 0x3528,
0xf0b1, 0x234c, 0xe6d5, 0xede7, 0x287e, 0xf93d, 0x3ca4, 0x3796, 0xf20f, 0x21f2, 0xe46b, 0xef59,
0x2ac0, 0xd3a, 0xc8a3, 0xc391, 0x608, 0xd5f5, 0x106c, 0x1b5e, 0xdec7, 0x54aa, 0x9133, 0x9a01,
0x5f98, 0x8c65, 0x49fc, 0x42ce, 0x8757, 0xa0ad, 0x6534, 0x6e06, 0xab9f, 0x7862, 0xbdfb, 0xb6c9,
0x7350, 0x51d6, 0x944f, 0x9f7d, 0x5ae4, 0x8919, 0x4c80, 0x47b2, 0x822b, 0xa5d1, 0x6048, 0x6b7a,
0xaee3, 0x7d1e, 0xb887, 0xb3b5, 0x762c, 0xfc41, 0x39d8, 0x32ea, 0xf773, 0x248e, 0xe117, 0xea25,
0x2fbc, 0x846, 0xcddf, 0xc6ed, 0x374, 0xd089, 0x1510, 0x1e22, 0xdbbb, 0xaf8, 0xcf61, 0xc453,
0x1ca, 0xd237, 0x17ae, 0x1c9c, 0xd905, 0xfeff, 0x3b66, 0x3054, 0xf5cd, 0x2630, 0xe3a9, 0xe89b,
0x2d02, 0xa76f, 0x62f6, 0x69c4, 0xac5d, 0x7fa0, 0xba39, 0xb10b, 0x7492, 0x5368, 0x96f1, 0x9dc3,
0x585a, 0x8ba7, 0x4e3e, 0x450c, 0x8095
};
#endif

2337
APP/ltc6813_comm.c Normal file
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58
APP/ltc6813_comm.h Normal file
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/**
******************************************************************************
* @file ltc6813_comm.h
* @author MCD Application Team
* @version V1.0.0
* @date 05/12/2011
* @brief This file contains all the functions prototypes for the ltc6813_comm.c
* file.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef LTC6813_COMM_H_
#define LTC6813_COMM_H_
/* Includes ------------------------------------------------------------------*/
#include <stm32f10x.h>
void App_TaskBatt(void);
uint16_t GetTempRawValue(uint8_t tNo);
void dec_cb_tick(u16 tick);
void clear_cb_value(void);
uint8_t GetCB_Rest(void);
void SetManualBalancing(uint8_t flag, uint8_t *data);
void inc_afe_bufftime(uint32_t tick);
uint32_t GetOneBuffTime(void);
uint32_t GetAllBuffTime(void);
uint8_t SetLtc6813_Param(uint8_t *text, uint8_t aDevice);
void ODisplayBalancingValue(uint8_t p);
uint32_t GetBalancingAvgVoltage(void);
extern uint8_t ManualBalFlag;
extern uint32_t ManualBalEnable;
extern uint32_t ManualBalMode;
extern uint32_t BalMode;
#endif
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

251
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/**
******************************************************************************
* File Name : screen.c
* Description : This file provides code for the string
* of debug console.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
#ifdef CONSOLE_DEBUG
/* Includes ------------------------------------------------------------------*/
#include <includes.h>
#include "delay.h"
#define SCREEN_LINE_DELAY 2 // line delay 2ms
const char OPMODE_STR[][84] =
{
// 1 2 3 4 5 6 7 8
// 123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890
"\r\n+--[Battery : ]---+---+---+---+---+---+---+---+---+---+--------------------+", // 2
"\r\n| HeartB ( ) | B |OCA|TCA|TDA|AFE|RSV|ZVC|F-C|F-D| Warning ( )HEX|", // 3
"\r\n+---------------------+ S |INI|MD |FC |FD |RXM|ZVC|F-C|F-D| Protection( )HEX|", // 4
"\r\n| B-Volt ( . )V |---+---+---+---+---+---+---+---+---+-[CELL AVG ]--------+", // 5
"\r\n| Current ( . )A | W |RSV|RSV|RSV|L-C|LTD|LTC|HTD|HTC| C-MAX ( . )V |", // 6
"\r\n| SOC ( . )% + N |RSV|RSV|OCD|OCC|CUV|SUV|COV|SOV| C-AVG ( . )V |", // 7
"\r\n+---------------------+---+---+---+---+---+---+---+---+---+ C-MIN ( . )V |", // 8
"\r\n| Operate( )| P |AFE|RSV|SC |RSV|LTD|LTC|HTD|HTC| C-DIFF ( . )V |", // 9
"\r\n| Status ( )| T |RSV|RSV|OCD|OCC|CUV|SUV|COV|SOV| CB AVG ( . )V |", // 0
"\r\n+--[Cell Volt]--------+---+---+---+---+---+---+---+---+---+ [ ] |", // 1
"\r\n|01( . ) 11( . )| M-FLAG( ) +-[TEMP AVG ]--------+", // 2
"\r\n|02( . ) 12( . )| M-BAL ( ) | T-MAX ( . )C |", // 3
"\r\n|03( . ) 13( . )| BAL-ST( ) | T-AVG ( . )C |", // 4
"\r\n|04( . ) 14( . )| | T-MIN ( . )C |", // 5
"\r\n|05( . ) 15( . )| MODE ( ) | T-DIFF ( . )C |", // 6
"\r\n|06( . ) 16( . )+---------+---------+---------+-----+---+-[CONFIG]-------+", // 7
"\r\n|07( . ) 17( . )|T1( . )|T3( . )|T5( . )|T7( . )| 0 ( ) ( ) |", // 8
"\r\n|08( . ) 18( . )| | | | | 1 ( ) ( ) |", // 9
"\r\n|09( . ) 19( . )|T2( . )|T4( . )|T6( . )|T8( . )| 2 ( ) ( ) |", // 0
"\r\n|10( . ) 20( . )| | | | | 3 ( ) ( ) |", // 1
"\r\n+---------------------+---------+---------+---------+---------+----------------+", // 2
"\r\n s : SETTING d : DIAGNOSTIC " // 3
};
void OmodeScreen(void)
{
for (int i = 0; i < 22; i++)
{
printf("%s", OPMODE_STR[i]);
delay_os_ms(SCREEN_LINE_DELAY);
}
}
const char SETMODE_STR[22][84] =
{
// 1 2 3 4 5 6 7 8
// 123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890
" mBMS [SETTING] MODE",
"\r\n+--[PARMAMETER]---------+------------------------------------------------------+",
"\r\n| '1': Safety Config | |",
"\r\n| '2': SBS Config | |",
"\r\n+-----------------------+ |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n+------------------------------------------------------------------------------+",
"\r\n 'o' : OPERATING 'd' : DIAGNOSTIC "
};
void SmodeScreen(void)
{
for (int i = 0; i < 22; i++)
{
printf("%s", SETMODE_STR[i]);
delay_os_ms(SCREEN_LINE_DELAY);
}
}
const char DIAGMODE_STR[22][84] = {
// 1 2 3 4 5 6 7 8
// 123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890
" mBMS [DIAGNOSTIC] MODE",
"\r\n+------------------------------------------------------------------------------+",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n|----------------------------< CAN COMM MONITOR >----------------------------|",
"\r\n| '2' : CAN MSG MONITOR ( ) '3' : CAN DATA MONITOR ( ) |",
"\r\n|------------------------------------------------------------------------------|",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n|---------------------------------------------------+--[SYSTEM CONTROL]--------+",
"\r\n| | 'q': S/W Reset |",
"\r\n| | |",
"\r\n| | |",
"\r\n| | |",
"\r\n| | |",
"\r\n+---------------------------------------------------+--------------------------+",
"\r\n o : OPERATING s: SETTING "
};
void DmodeScreen(void)
{
u16 i;
for (i = 0; i < 22; i++)
{
printf("%s", DIAGMODE_STR[i]);
delay_os_ms(SCREEN_LINE_DELAY);
}
}
const char TASK_STS_MODE_STR[22][84] =
{
// 1 2 3 4 5 6 7 8
// 123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890
" mBMS [OS TASK STATUS] MODE",
"\r\n+------------------------------------------------------------------------------+",
"\r\n| uC/OS-III, The Real-Time Kernel |",
"\r\n| Modify by JKWoo In Amogreentech |",
"\r\n|------------------------------------------------------------------------------|",
"\r\n| Task TStack FStack UStack CPU Us Peak ExecTime (mS) |",
"\r\n|-------------- ------ ------ ------ ------ ------ ------------- |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n|------------------------------------------------------------------------------|",
"\r\n| #Tasks : #CPU Usage: % #Task switch/sec: |",
"\r\n+------------------------------------------------------------------------------+",
"\r\n o : OPERATING s: SETTING "
};
void OSmodeScreen(void)
{
for (int i = 0; i < 22; i++)
{
printf("%s", TASK_STS_MODE_STR[i]);
delay_os_ms(SCREEN_LINE_DELAY);
}
}
const char SF1_SET_STR[22][84] =
{
// 1 2 3 4 5 6 7 8
// 123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890
" mBMS [SAFETY] MODE",
"\r\n+--[1ST LEVEL SAFETY ]---------------------------------------------------------+",
"\r\n+-[VOLTAGE : '1' ]---------+-[TEMP : '3']------------+-[S VOLTAGE : '4']------+",
"\r\n| '1': COV Protect( )mV | '1': OT Chg Pro( . )C | '1': SOV Protect( )V |",
"\r\n| '2': COV Warning( )mV | '2': OT Chg War( . )C | '2': SOV Warning( )V |",
"\r\n| '3': COV Recover( )mV | '3': OT Chg Rec( . )C | '3': SOV Recover( )V |",
"\r\n|--------------------------|-------------------------|-------------------------|",
"\r\n| '4': CUV Protect( )mV | '4': OT Dsg Pro( . )C | '4': SUV Protect( )V |",
"\r\n| '5': CUV Warning( )mV | '5': OT Dsg War( . )C | '5': SUV Warning( )V |",
"\r\n| '6': CUV Recover( )mV | '6': OT Dsg Rec( . )C | '6': SUV Recover( )V |",
"\r\n+--------------------------+-------------------------+-------------------------+",
"\r\n| | '7': LT Chg Pro( . )C | |",
"\r\n| | '8': LT Chg War( . )C | |",
"\r\n| | '9': LT Chg Rec( . )C +-[CELL DIFF : '6']------+",
"\r\n| |-------------------------| '1': CVD Protect( )mV|",
"\r\n+-[Balance Cfg : '2']-----+ 'a': LT Dsg Pro( . )C | '2': CVD Warning( )mV|",
"\r\n| '1': C-Bal Thr ( )mV | 'b': LT Dsg War( . )C | '3': CVD Recover( )mV|",
"\r\n| '2': C-Bal Win ( )mV | 'c': LT Dsg Rec( . )C +-[Thermistor : '7']------+",
"\r\n| '3': C-Bal Min ( )mV +-------------------------+ '1': Therm Open( . )C |",
"\r\n| '4': C-Bal Int ( )S | | '2': Therm Reco( . )C |",
"\r\n+--------------------------+-------------------------+-------------------------+",
"\r\n 'o' : OPERATING 'd' : DIAGNOSTIC "
};
void SF1modeScreen(void)
{
for (int i = 0; i < 22; i++)
{
printf("%s", SF1_SET_STR[i]);
delay_os_ms(SCREEN_LINE_DELAY);
}
}
const char SBS_SET_STR[22][84] =
{
// 1 2 3 4 5 6 7 8
// 123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890
" mBMS [SBS Configuration] MODE",
"\r\n+-[Data : '1']------------+---------------------------------------------------+",
"\r\n| '1': Dev Addr ( ) | |",
"\r\n+-[Offset: '2']------------+ |",
"\r\n| '1': CV-LOW ( ) | |",
"\r\n| '2': CV-HIGH ( ) | |",
"\r\n+--------------------------+ |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n| |",
"\r\n+------------------------------------------------------------------------------+",
"\r\n 'o' : OPERATING 'd' : DIAGNOSTIC "
};
void SBSmodeScreen(void)
{
for (int i = 0; i < 22; i++)
{
printf("%s", SBS_SET_STR[i]);
delay_os_ms(SCREEN_LINE_DELAY);
}
}
#endif //CONSOLE_DEBUG

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/**
******************************************************************************
* File Name : screen.h
* Description : This file provides code for the string
* of debug console.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
#ifdef CONSOLE_DEBUG
#ifndef _SCREEN_H_
#define _SCREEN_H_
void OmodeScreen(void);
void SmodeScreen(void);
void DmodeScreen(void);
void OSmodeScreen(void);
void SF1modeScreen(void);
void SBSmodeScreen(void);
#endif
#endif

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/**
******************************************************************************
* @file task_manager.c
* @author MSO Application Team
* @version V1.0.0
* @date 10-October-2011
* @brief This file provides all the memory related operation functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2015 MSO</center></h2>
******************************************************************************
*/
/** @addtogroup BMCU(EMCB)
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include "includes.h"
#include "asutil.h"
#include "console.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define OS_MAX_TASK_PRIO 9
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
OS_TCB AppTaskTCB[OS_MAX_TASK_PRIO - 3]; // 0 ~ 2 Task -> uC/OS
u16 disCPU_Usage[OS_MAX_TASK_PRIO - 3];
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
void TaksTCBInit(void)
{
memset(AppTaskTCB, 0x00, sizeof(OS_TCB) * (OS_MAX_TASK_PRIO - 3));
}
void *GetAppTaskTCB(u16 prio)
{
return &AppTaskTCB[prio - 3];
}
#ifdef CONSOLE_DEBUG
/* Task Status Mode STATE에서 명령어 처리 */
s8 Process_TaskStatus_Data(u8 *text, u16 size)
{
s8 ret;
if (size > 1) {
if(text[1] != ' ') return(0); /* 첫칸에 space 포함되어있으면 Invalid command */
}
text[size] = 0x00;
ret = 1;
switch (text[0]) {
case 'o':
screenmode = OP_MODE;
ViewScreen();
break;
case 's':
screenmode = SET_MODE;
ViewScreen();
break;
case 'd':
screenmode = DIAG_MODE;
ViewScreen();
break;
default:
ret = 0;
break;
}
return(ret);
}
u32 disCPUSum;
u32 bakOSTaskCtxSwCtr;
u32 PerSecOSTaskCtxSwCrt;
u32 disOSTaskCtxSwCtr;
u32 cswTick = 0;
void CalOSTaskCtxSwCtrPerSec(u32 tick)
{
cswTick += tick;
if (cswTick >= 1000)
{
PerSecOSTaskCtxSwCrt = OSTaskCtxSwCtr - bakOSTaskCtxSwCtr;
bakOSTaskCtxSwCtr = OSTaskCtxSwCtr;
cswTick = 0;
}
}
void osDisplayTaskStatus(u8 p)
{
u32 CPUSum = 0;
uint8_t text[100];
static u32 tsCount = 0;
if (p || (tsCount <= 0))
{
for (int i = 0; i < OS_MAX_TASK_PRIO - 3; i++)
{
if (AppTaskTCB[i].StkPtr == NULL) continue;
if (p)
{
sprintf((char *)text, "%s", AppTaskTCB[i].NamePtr);
NormalOutXY( 2, 8 + i, text);
}
if (p)
{
sprintf((char *)text, "%6d %6d %6d",
AppTaskTCB[i].StkSize,
AppTaskTCB[i].StkFree,
AppTaskTCB[i].StkUsed
);
NormalOutXY( 18, 8 + i, text);
}
if (p ||(disCPU_Usage[i] != AppTaskTCB[i].CPUUsage))
{
uint8_t a[12];
uint8_t b[12];
FloatToStr((float)AppTaskTCB[i].CPUUsage / 100, a, 6, 2);
FloatToStr((float)AppTaskTCB[i].CPUUsageMax / 100, b, 6, 2);
sprintf((char *)text, "%s(%s)", a, b);
NormalOutXY( 18 + 24, 8 + i, text);
disCPU_Usage[i] = AppTaskTCB[i].CPUUsage;
}
if (p)
{
sprintf((char *)text, "%6d", AppTaskTCB[i].TickRemain);
NormalOutXY( 64, 8 + i, text);
}
CPUSum += AppTaskTCB[i].CPUUsage;
}
if (p ||(disCPUSum != CPUSum))
{
FloatToStr((float)CPUSum / 100, text, 5, 1);
GreenOutXY( 42, 20, text);
disCPUSum = CPUSum;
}
if (p || (disOSTaskCtxSwCtr != PerSecOSTaskCtxSwCrt))
{
sprintf((char *)text, "%6d", PerSecOSTaskCtxSwCrt);
GreenOutXY( 70, 20, text);
disOSTaskCtxSwCtr = PerSecOSTaskCtxSwCrt;
}
tsCount = 200;
}
tsCount--;
}
#endif // #ifdef CONSOLE_DEBUG
/*******************(C)COPYRIGHT 2015 MSO ********************END OF FILE******/

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/**
******************************************************************************
* @file task_manager.h
* @author MSO Application Team
* @version V1.0.0
* @date 10-October-2011
* @brief This file provides all the headers of the flash_if functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2015 MSO</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TASK_MANAGER_H
#define __TASK_MANAGER_H
/* Includes ------------------------------------------------------------------*/
#include "sys.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void TaksTCBInit(void);
void *GetAppTaskTCB(u16 prio);
s8 Process_TaskStatus_Data(u8 *text, u16 size);
void osDisplayTaskStatus(u8 p);
void CalOSTaskCtxSwCtrPerSec(u32 tick);
#endif /* __TASK_MANAGER_H */
/*******************(C)COPYRIGHT 2015 MSO ********************END OF FILE******/

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/**
******************************************************************************
* File Name : temp.c
* Description : This file provides code for the measument of voltage
and current.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include <includes.h>
#include "delay.h"
#include "device_param.h"
#include "asutil.h"
#include "temp.h"
#include "ltc6813_comm.h"
/* Private typedef -----------------------------------------------------------*/
typedef struct
{
s16 Value;
s16 AdValue;
// PARAMETER Information
s16 HighParam; // 온도Parameter는 AD[4](Unify-Temp)에서만 참조된다
s16 HighCParam;
s16 LowParam;
s16 LowCParam;
s16 FailParam;
s16 FailCParam;
u8 Enabled; // Enabled/Disabled
u8 Failed; // Fail/Noraml
u8 State; // 정상,고온(습),저온,NotUsed (0/1/2/3)
u8 Changed; // notchanged,적온->고온,고온->적온,적온->저온,저온->적온,NotUsed->Used,Used->NotUsed,Normal->Failed,Failed->Normal
} TAnalogrec, *PAnalogrec;
typedef struct
{
s16 temp;
u16 vref;
u16 vbat;
u16 reserved;
} TCPUStatus, *PCPUStatus;
/* Private define ------------------------------------------------------------*/
#define TEMP_TASK_TIME 50 // 100ms TASK
#define AD_TEMP_CH_MAX 8
#define TEMP_CH_MAX 8
#define T1_TEMP_ID 0
#define T2_TEMP_ID 1
#define T3_TEMP_ID 2
#define T4_TEMP_ID 3
#define T5_TEMP_ID 4
#define T6_TEMP_ID 5
#define T7_TEMP_ID 6
#define T8_TEMP_ID 7
#define TEMP_BUF_MAX 10
// Temperature alarm flag define
#define cFahr 0x00
#define cCent 0x01
#define cHighOccur 0x01 // 정상->고온(습)
#define cLowOccur 0x02 // 정상->저온
#define cNotUsed 0x03 // Disabled
#define cNotChanged 0x00 // 변화없음
#define cNormToHigh 0x11 // 정상->고온(습)
#define cHighToNorm 0x12 // 고온(습)->정상
#define cNormToLow 0x13 // 정상->저온
#define cLowToNorm 0x14 // 저온->정상
#define cNotToUsed 0x15 // NotUsed->Used
#define cUsedToNot 0x16 // Used->NotUsed
#define cFailToNorm 0x17 // Fail->Normal
#define cNormToFail 0x18 // Normal->Fail
#define cNormalOpen 0
#define cNormalClose 1
#define cNORMAL 0
#define cINITVALUE 0xff
#define cOCCUR 1
#define cUNKNOWN 2
#define cDISABLE 3
#define cCANCEL 0
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
// ADC Buffer
u16 AdData[AD_TEMP_CH_MAX][TEMP_BUF_MAX];
u16 AdCh = 0;
// Temperature Buffer
TAnalogrec TD[TEMP_CH_MAX];
TAnalogrec DisTD[TEMP_CH_MAX];
u8 TempUnit, BakTempUnit;
void AdcInit(void);
void InitAD(u8 ch);
void ADC_Data_Process(void);
s16 GetTemperature(u8 ch);
s16 CalcTemperatureST32(u16 volt);
/*
*********************************************************************************************************
* App_TaskAdc Init
*
* Description : ADC TASK INIT
*
*********************************************************************************************************
*/
void AdcInit(void)
{
// ADC initialization
// ADC Clock frequency: 115.200 kHz
// ADC Voltage Reference: Vref Pin
// ADC High Speed Mode: On
memset(AdData, 0x00, sizeof(AdData));
memset(TD , 0x00, sizeof(TAnalogrec) * TEMP_CH_MAX);
TempUnit = cCent;
for (int i = 0; i < TEMP_CH_MAX; i++)
InitAD(i);
}
/*
*********************************************************************************************************
* Function for App_TaskAdc
*
* Description : ADC TASK
*
*********************************************************************************************************
*/
void App_TaskTemp(void)
{
AdcInit();
while (DEF_TRUE)
{
ADC_Process();
delay_os_ms(TEMP_TASK_TIME);
}
}
void InitAD(u8 ch)
{
for (int i = 0; i < 20; i++)
{
TD[ch].Value = GetTemperature(ch);
}
TD[ch].Enabled = true;
TD[ch].Failed = false;
TD[ch].State = cNORMAL;
TD[ch].Changed = cNotChanged;
}
void ADC_Data_Process(void)
{
for (int i = 0; i < AD_TEMP_CH_MAX; i++)
{
AdData[i][AdCh] = GetTempRawValue(i) / 10;
}
AdCh++;
AdCh %= TEMP_BUF_MAX;
}
s16 CalcTemperatureNTC(u16 volt, u16 beta)
{
// double beta1 = 3380;
// double beta2 = 3950;
double Rnom = 10000;
double Koffset = 273.16;
double Tnom = 25 + Koffset;
double R1 = 10 * 1000;
double Vref = 3.0;
// R2 = V * R1 / (Vref - V) # Calculate resistance value of NTC
// V = R1 / (R1 + R2) * Vref --> V * R1 + V * R2 = Vref * R1 --> V * R2 = (Vref * R1) - (V * R1) --> R2 = (Vref * R1) / V - R1
// V = R2 / (R1 + R2) * Vref --> (V * R1) + (V * R2) = (Vref * R2) --> (Vref * R2) - (V * R2) = (V * R1) --> R2 = (V * R1)/(Vref - V) * NTC Bottom side
// V = RL / (R1 + RL) * Vref --> V * (R1 + RL) = Vref * RL --> VR1 + VRL = VrefRL --> VrefRL - VRL = VR1 --> (Vref - V)RL = VR1 --> RL = (V * R1)/(Vref - V)
// RL = (V * R1)/(Vref - V)
double V = (double)volt / 1000;
double RL = (V * R1) / (Vref - V);
double T = (beta * Tnom / (Tnom * log(RL / Rnom) + beta)) - Koffset; // # Calculate corresponding temperature (above shortened)
return (s16)(T * 10);
}
// y = -8.1415x5 + 65.574x4 - 207.39x3 + 323.01x2 - 286.28x + 157.85 ; R² = 0.9998
s16 CalcTemperatureST32(u16 volt)
{
// s16 cvolt;
double imsi;
double xx[6];
double flt;
// cvolt = volt;
imsi = (double)volt / 1000;
xx[5] = imsi * imsi * imsi * imsi * imsi;
xx[4] = imsi * imsi * imsi * imsi;
xx[3] = imsi * imsi * imsi;
xx[2] = imsi * imsi;
xx[1] = imsi;
flt = ( -8.1415 * xx[5]) +
( 65.5740 * xx[4]) +
(-207.3900 * xx[3]) +
( 323.0100 * xx[2]) +
(-286.2800 * xx[1]) +
157.8500;
return(s16)(flt * 10);
}
s16 GetTemperature(u8 ch)
{
s32 tsum = 0;
for (int i = 0; i < TEMP_BUF_MAX; i++)
{
tsum += CalcTemperatureST32(AdData[ch][i]);
// tsum += CalcTemperatureNTC(AdData[ch][i], 3435);
}
return (s16)(tsum / TEMP_BUF_MAX);
}
void ADC_Param_Load(void)
{
for (int i = 0; i < TEMP_CH_MAX; i++)
{
TD[i].HighParam = device_param.safety.temperature.OT_Chg_Warning;
TD[i].HighCParam = device_param.safety.temperature.OT_Chg_Recovery;
TD[i].LowParam = device_param.safety.temperature.LT_Chg_Warning;
TD[i].LowCParam = device_param.safety.temperature.LT_Chg_Recovery;
TD[i].FailParam = device_param.safety.temperature.Open_Thermistor;
TD[i].FailCParam = device_param.safety.temperature.Recovery_Thermistor;
}
}
u8 Check_Analog(u8 ch)
{
s16 aValue, ret, aHighOccur, aHighCancel, aLowOccur, aLowCancel;
switch (ch)
{
case T1_TEMP_ID:
case T2_TEMP_ID:
case T3_TEMP_ID:
case T4_TEMP_ID:
case T5_TEMP_ID:
case T6_TEMP_ID:
case T7_TEMP_ID:
case T8_TEMP_ID:
aValue = TD[ch].Value;
aHighOccur = TD[ch].HighParam;
aHighCancel = TD[ch].HighCParam;
aLowOccur = TD[ch].LowParam;
aLowCancel = TD[ch].LowCParam;
break;
default:
return 0;
}
ret = cNotChanged; // Nothing
switch(TD[ch].State) // 과거 상태
{
case cHighOccur: // 과거:고온(습)
if (aValue < aHighCancel) ret = cHighToNorm; // HIGH CANCEL
break;
case cLowOccur: // 과거:저온
if (aValue > aLowCancel) ret = cLowToNorm; // LOW CANCEL
break;
default:
if (aValue >= aHighOccur) ret = cHighOccur; // HIGH OCCUR
else if (aValue <= aLowOccur) ret = cLowOccur; // LOW OCCUR
break;
}
return(ret);
}
void Analog_Process(u8 ch) // 현재의 온,습도값을 가져와 경보를 분석한다.
{
TD[ch].Value = GetTemperature(ch);
if(TD[ch].Enabled == true)
{
// Check sensor fail on low temperature range
if (TD[ch].Failed != true)
{
if ((TD[ch].Value < TD[ch].FailParam) || (TD[ch].Value > 1250))
{
TD[ch].State = cNORMAL;
TD[ch].Changed = cNormToFail;
TD[ch].Failed = true;
}
}
else
{
if ((TD[ch].Value > TD[ch].FailCParam) && (TD[ch].Value < 1200))
{
TD[ch].State = cNORMAL;
TD[ch].Changed = cFailToNorm;
TD[ch].Failed = false;
}
}
// Check temperature alarm
if (TD[ch].Failed == false)
{
switch (Check_Analog(ch))
{
case cHighOccur: // HIGH OCCUR
TD[ch].State = cHighOccur;
TD[ch].Changed = cNormToHigh;
break;
case cHighToNorm: // HIGH CANCEL
TD[ch].State = cNORMAL;
TD[ch].Changed = cHighToNorm;
break;
case cLowOccur: // LOW OCCUR
TD[ch].State = cLowOccur;
TD[ch].Changed = cNormToLow;
break;
case cLowToNorm: // LOW CANCEL
TD[ch].State = cNORMAL;
TD[ch].Changed = cLowToNorm;
break;
}
}
}
else
TD[ch].State = cNotUsed;
}
u16 ADState(u8 ch)
{
u16 ret = AD_DISABLE;
if (TD[ch].Enabled == true)
{
if (TD[ch].Failed == true)
{
ret = AD_FAIL;
}
else
{
switch (TD[ch].State)
{
case cHighOccur:
ret = AD_HIGH;
break;
case cLowOccur:
ret = AD_LOW;
break;
case cNORMAL :
ret = AD_NORMAL;
break;
default :
ret = AD_NORMAL;
break;
}
}
}
return ret;
}
s16 TEMP_GRADE_CONVERTOR(s16 aTempValue, u8 aGrade)
{
s16 Tf, Tc;
if (aGrade == 'F')
{
Tc = aTempValue;
Tf = (18 * Tc)/10 + 320; // 섭씨를 화씨로
return(Tf);
}
else
{
Tf = aTempValue;
Tc = (Tf - 320)/18;
return(Tc);
}
/*
섭씨를 화씨로 바꾸는 공식: Tf = 9/5 * Tc +32
화씨를 섭씨로 바꾸는 공식: Tc = (Tf - 32) * 5/9
*/
}
s16 ADValue(u8 ch)
{
s16 result = 0;
switch (ch)
{
case T1_TEMP_ID :
case T2_TEMP_ID :
case T3_TEMP_ID :
case T4_TEMP_ID :
case T5_TEMP_ID :
case T6_TEMP_ID :
case T7_TEMP_ID:
case T8_TEMP_ID:
if (TempUnit == cCent) result = TD[ch].Value;
else result = TEMP_GRADE_CONVERTOR(TD[ch].Value,'F');
break;
}
return result;
}
float ADValueF(u8 ch)
{
float result = 0.0;
switch (ch)
{
case T1_TEMP_ID :
case T2_TEMP_ID :
case T3_TEMP_ID :
case T4_TEMP_ID :
case T5_TEMP_ID :
case T6_TEMP_ID :
case T7_TEMP_ID:
case T8_TEMP_ID:
result = (float)TD[ch].Value / 10;
break;
}
return result;
}
void TEMPERATURE_Process(u8 ch)
{
u8 aAlarm;
aAlarm = TD[ch].State;
switch (TD[ch].Changed)
{
case cHighToNorm :
aAlarm = cNORMAL;
break;
case cLowToNorm :
aAlarm = cNORMAL;
break;
case cNormToHigh :
aAlarm = cHighOccur;
break;
case cNormToLow :
aAlarm = cLowOccur;
break;
case cNormToFail :
aAlarm = cNORMAL;
break;
case cFailToNorm :
aAlarm = cNORMAL;
break;
}
if (TD[ch].Enabled != true)
aAlarm = cNORMAL;
TD[ch].State = aAlarm;
}
void Analog_Event_Process(u8 ch)
{
switch (ch)
{
case T1_TEMP_ID:
case T2_TEMP_ID:
case T3_TEMP_ID:
case T4_TEMP_ID:
case T5_TEMP_ID:
case T6_TEMP_ID:
case T7_TEMP_ID:
case T8_TEMP_ID:
TEMPERATURE_Process(ch);
break;
}
}
void CalcAvgTemperature(void)
{
u32 sum;
TTempMinMax min, max;
sum = 0;
max.value = 0;
max.num = 0;
min.value = 0;
min.num = 0;
int j = 0;
for (int i = 0; i < (TEMP_CH_MAX - 2); i++)
{
if (TD[i].Failed == false)
{
if (j == 0)
{
max.value = ADValue(i);
max.num = i;
min.value = ADValue(i);
min.num = i;
}
if (max.value < ADValue(i))
{
max.value = ADValue(i);
max.num = i;
}
if (min.value > ADValue(i))
{
min.value = ADValue(i);
min.num = i;
}
sum += ADValue(i);
j++;
}
}
if (j == 0)
device_value.Temp.avg.avg = 0;
else
device_value.Temp.avg.avg = sum / j;
device_value.Temp.avg.Max.value = max.value;
device_value.Temp.avg.Max.num = max.num;
device_value.Temp.avg.Min.value = min.value;
device_value.Temp.avg.Min.num = min.value;
device_value.Temp.avg.diff = max.value - min.value;
}
void ADC_Get_Process(u8 ch)
{
TD[ch].Changed = cNotChanged; // Changed_Member 초기화
Analog_Process(ch);
Analog_Event_Process(ch);
}
void ADC_Process(void)
{
ADC_Data_Process();
for (int i = 0; i < (TEMP_CH_MAX - 0); i++)
{
ADC_Get_Process(i);
device_value.Temp.temperature[i] = ADValue(i);
delay_os_ms(1);
}
CalcAvgTemperature();
}
#ifdef CONSOLE_DEBUG
void ODisplayAdcStatus(u8 p)
{
u16 i, x, y;
float aParam;
u8 aRedFont;
static int tcount = 0;
// TEMP DISPLAY
if (p || (tcount == 0))
{
tcount = 10;
for (i = 0; i < (TEMP_CH_MAX); i++)
{
if (p || (memcmp(&TD[i], &DisTD[i], sizeof(TAnalogrec)) != 0))
{
x = 27 + ((i / 2)* 10);
y = 18 + ((i % 2)* 2);
if ((TD[i].Enabled == true) & ((TD[i].State != cNORMAL) | (TD[i].Failed == true)))
aRedFont = DISPLAY_RED;
else
aRedFont = DISPLAY_GREEN;
if (TD[i].Failed == true)
{
aParam = (float)ADValue(i) / 10;
FloatColorOutIntXY(aRedFont, x, y, aParam, 5, 1);
if (p || (TD[i].Failed != DisTD[i].Failed))
ColorOutXY(aRedFont, x + 1, y + 1, (u8 *)"FAIL");
}
else
{
aParam = (float)ADValue(i) / 10;
FloatColorOutIntXY(aRedFont, x, y, aParam, 5, 1);
if (p || (TD[i].State != DisTD[i].State)||(TD[i].Failed != DisTD[i].Failed))
{
switch (TD[i].State)
{
case cHighOccur: ColorOutXY(aRedFont, x + 1, y + 1, (u8 *)"HIGH");
break;
case cLowOccur: ColorOutXY(aRedFont, x + 1, y + 1, (u8 *)"LOW ");
break;
case cNORMAL : ColorOutXY(aRedFont, x + 1, y + 1, (u8 *)"NORM");
break;
default : ColorOutXY(aRedFont, x + 1, y + 1, (u8 *)"????");
break;
}
}
}
memcpy(&DisTD[i], &TD[i], sizeof(TAnalogrec));
}
}
}
tcount--;
}
#endif // #ifdef CONSOLE_DEBUG

39
APP/temp.h Normal file
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/*
*********************************************************************************************************
*
* APPLICATION CONFIGURATION
*
* ST Microelectronics STM32
* with the
* BMCU for AMO LFP 380-100
*
* Filename : adc.h
* Version : V1.00
* Programmer(s) : JK.Woo
*********************************************************************************************************
*/
#ifndef _TEMP_H_
#define _TEMP_H_
#include <stm32f10x.h>
#define AD_NORMAL 0x0000
#define AD_DISABLE 0x0000
#define AD_FAIL 0x0001
#define AD_HIGH 0x0002
#define AD_LOW 0x0003
void App_TaskTemp(void);
void ADC_Process(void);
void ADC_Param_Load(void);
float ADValueF(u8 ch);
s16 ADValue(u8 ch);
u16 ADState(u8 ch);
void ODisplayAdcStatus(u8 p);
#endif

784
CORE/core_cm3.c Normal file
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/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

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;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD OS_CPU_PendSVHandler ; PendSV Handler
DCD OS_CPU_SysTickHandler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
OS_CPU_PendSVHandler\
PROC
EXPORT OS_CPU_PendSVHandler [WEAK]
B .
ENDP
OS_CPU_SysTickHandler\
PROC
EXPORT OS_CPU_SysTickHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

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# 9번 셀 밸런싱 비동작 원인 분석 보고서 (회로도 및 하드웨어 연계 분석)
제공해주신 회로도 PDF [001 CPU.SchDoc] 및 [003 AFE.SchDoc] 문서를 면밀히 분석한 결과, **수동 밸런싱 테스트에서 9번 셀만 동작하지 않는 문제의 하드웨어적 원인과 소프트웨어적 해결 방법**을 명확히 규명하였습니다.
---
## 1. 회로도 분석 결과 (핀 매핑 확인)
* **회로도 상 연결**:
- [001 CPU] 페이지의 **U1 (STM32F103CBT6)** 핀 맵에서 9번 셀 밸런싱 제어 네트인 `MCU_EN9/S9`는 **Pin 6 (`PD1/OSC_OUT`)**에 정상적으로 연결되어 있습니다.
- 또한, [008 Enable Control] 페이지에서도 `MCU_EN9/S9` 신호가 9번 셀 밸런싱용 스위칭 FET인 `Q27 (AM2336N)`의 게이트(Gate)를 제어하고 있습니다.
- 회로 상에서는 연결에 문제가 없는 설계입니다.
* **클럭 발진 회로 구성**:
- [001 CPU] 페이지 하단에 16MHz 클럭 발진부인 **`Y1` (SCO-103 16MHz)**이 배치되어 있습니다.
- 이 소자는 2핀 크리스탈이 아닌, 전원을 받아 스스로 클럭을 출력하는 **4핀 액티브 오실레이터 (Active Oscillator)**입니다.
- `Y1`의 3번 출력 핀(`OUTPUT`)은 MCU의 **Pin 5 (`PD0/OSC_IN`)**에 단독으로 클럭을 주입하고 있으며, 피드백 출력 핀인 **Pin 6 (`PD1/OSC_OUT`)**은 비어 있는 상태로 일반 GPIO로 활용하도록 설계되었습니다.
---
## 2. 근본적인 오동작 원인 (두 가지 조건 불충족)
STM32F10x MCU에서 `PD0` 및 `PD1` 핀을 클럭 오실레이터가 아닌 일반 GPIO 포트로 사용하기 위해서는 **반드시 아래 2가지 설정이 동시에 활성화**되어야 합니다.
1. **HSE Bypass 모드 활성화 (클럭 점유 해제)**:
- 기본 설정인 **HSE Crystal 모드**가 활성화되면 MCU 내부의 발진 회로가 활성화되어 `PD0 (OSC_IN)`과 `PD1 (OSC_OUT)` 두 핀을 모두 발진용으로 강제 점유합니다.
- 외부 액티브 오실레이터처럼 이미 주입되는 클럭이 있는 환경에서는 **HSE Bypass 모드**를 켜주어야 `PD1` 핀이 클럭 공급 기능에서 해방됩니다.
2. **AFIO PD0/PD1 리맵 설정 (GPIO 포트 전환)**:
- 하드웨어적으로 클럭 점유가 해제되더라도, AFIO(Alternative Function IO) 레지스터 상에서 `PD0`과 `PD1` 핀을 일반 GPIO 포트로 사용하겠다고 맵핑을 직접 변경해주어야 합니다.
- 이 설정이 누락될 경우 핀이 GPIO 입력/출력 레지스터와 물리적으로 연결되지 않아 밸런싱 활성화 신호가 나가지 않습니다.
---
## 3. 해결 방안 (소프트웨어 조치 완료)
하드웨어 개조 없이 소프트웨어 설정 변경을 통해 버그 수정을 완료하였습니다.
### 단계 1: 시스템 클럭 설정 코드 수정 (`system_stm32f10x.c`)
시스템 클럭을 72MHz로 설정하는 `SetSysClockTo72()` 함수 내부에서 **HSE Bypass(Bypassed) 설정을 추가**하였습니다.
* **수정 내역**:
```c
/* Enable HSE Bypass and then enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEBYP); // <-- Bypass 활성화 추가
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
```
### 단계 2: AFIO 클럭 활성화 및 PD0/PD1 리맵핑 추가 (`led.c`)
`led.c`의 GPIO 초기화 함수인 `DIO_Init()` 내부에서 AFIO 주변장치 클럭을 활성화하고, `GPIO_Remap_PD01` 리맵 설정을 추가하였습니다.
* **수정 내역**:
```c
/* GPIO clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // <-- AFIO 클럭 추가
//Serial port 1 pins reuse maps
GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable, ENABLE);
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE); // <-- PD0/PD1 리맵 추가
```

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# Implementation Plan: 21S Active Balancing Firmware
## 1. Objective
Port the active balancing functionality from the 18S reference firmware to the current 21S project, ensuring correct hardware control and build stability.
## 2. Requirements
- Implement active balancing logic (Buck/Boost between adjacent cells).
- Map 20 balancing control channels to STM32 GPIOs based on schematic.
- Maintain compatibility with existing CAN communication and status reporting.
- Record all changes in `Revision History.txt`.
## 3. Implementation Steps
### Phase 1: Infrastructure and Data Structures (Completed)
- [x] Define `TBalanceEnable` union for 20 channels in `device_param.h`.
- [x] Add `balance_enable` field to `TDEVICE_STATUS`.
- [x] Update `ltc6813_comm.h` with new function prototypes.
- [x] Add `MP2642` control prototypes to `io.h`.
### Phase 2: Hardware Mapping (Completed)
- [x] Extract GPIO mapping for `MCU_EN1`~`MCU_EN20` from schematic.
- [x] Update `led.h` with accurate pin definitions.
- [x] Update `led.c` (`DIO_Init`) to initialize all balancing pins.
- [x] Implement `MP2642_Enable_Ctrl` and `MP2642_EnaDis_All` in `io.c`.
### Phase 3: Core Logic Porting (Completed)
- [x] Port `AutoBalancingActive`, `CalcBalancingVolt`, and `CheckCbRest` to `ltc6813_comm.c`.
- [x] Integrate `AutoBalancingActive` into `App_TaskBatt`.
- [x] Update manual balancing control to support active balancing FETs.
- [x] Fix undefined variable build errors (`ManualMdBalEnable`, `ManualMdBalMode`).
### Phase 4: Verification and Polish (Next Steps)
- [ ] Perform full build and verify zero errors/warnings.
- [ ] Verify `CB_Rest` rotation logic (Odd/Even channels) via debug logs or LEDs.
- [ ] Finalize `Revision History.txt` documentation.
## 4. Documentation Management
- All plans and design documents will be stored in the `/DOC` folder.
- `Revision History.txt` will be updated for every version change.

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# Project Improvement Suggestions: BMU 21S Application
Based on the analysis of the current codebase, the following improvements are suggested to enhance the system's stability, reliability, and maintainability.
## 1. Critical Reliability & Stability Improvements
### 1.1 Removal of Dynamic Memory Allocation (`malloc`/`free`)
- **Issue:** In `APP/battery_comm.c` (e.g., `ltc6813_wrcfg`, `ltc6813_rdcfg`), `malloc` and `free` are used inside functional calls.
- **Risk:** In an embedded RTOS environment, frequent dynamic allocation can lead to **heap fragmentation** and unpredictable `NULL` returns, potentially causing system crashes.
- **Recommendation:** Replace dynamic buffers with **static buffers** or **pre-allocated memory pools** since the maximum number of ICs in the daisy chain is typically constant.
### 1.2 Robust Error Handling for SPI/CAN Communication
- **Issue:** Many communication functions (e.g., `request_battery_voltage`) send commands but do not verify if the response is valid or if the hardware encountered an error.
- **Risk:** The system may process "garbage" data as valid cell voltages, leading to incorrect battery state estimation or failure to trigger alarms.
- **Recommendation:**
- Implement **return value checks** for all SPI/CAN read/write operations.
- Strictly enforce **PEC (Packet Error Code)** verification for every single packet received from LTC6813.
- Implement a **retry mechanism** (e.g., 3 attempts) before flagging a communication failure.
### 1.3 Improvement of `send_wakeup_signal` Logic
- **Issue:** `send_wakeup_signal` is called frequently (e.g., inside `App_TaskBatt` loop and multiple times in `request_battery_voltage`).
- **Risk:** Excessive wakeup signals may increase power consumption or interfere with the IC's internal state machine.
- **Recommendation:** Implement a **state-aware wakeup** mechanism that only sends the signal when the IC is actually in sleep mode or after a specific timeout.
## 2. Performance & Architecture Optimization
### 2.1 Task Priority Re-evaluation
- **Current State:**
- `BATT task` (Prio 3) $\rightarrow$ Highest
- `CAN Comm Task` (Prio 4)
- `Temp task` (Prio 5)
- `IO task` (Prio 6)
- **Analysis:** While battery monitoring is critical, CAN communication (handling requests and sending alarms) is also time-sensitive.
- **Recommendation:** Evaluate if `CAN Comm Task` needs a higher priority to ensure timely response to host commands, especially during critical fault conditions.
### 2.2 Use of DMA for Communication
- **Issue:** SPI and CAN operations currently appear to be synchronous/blocking (e.g., `SPI2_ReadWriteByte`).
- **Risk:** The CPU wastes cycles waiting for slow peripheral hardware, increasing CPU load.
- **Recommendation:** Implement **DMA (Direct Memory Access)** for SPI and CAN transfers to allow the CPU to perform other calculations while data is being moved.
## 3. Maintainability & Code Quality
### 3.1 Elimination of "Magic Numbers"
- **Issue:** Many hard-coded hex values are used for commands and PECs (e.g., `0x77D6`, `0xEA80` in `battery_comm.c`).
- **Recommendation:** Define these as **named constants** or macros in a header file (e.g., `#define LTC6813_CMD_RDCVA_PEC 0x77D6`) to improve readability and ease of modification.
### 3.2 Centralized Error Logging
- **Issue:** Debugging currently relies on `printf` and `NormalOutXY` scattered across the code.
- **Recommendation:** Implement a **centralized logging module** with different levels (`INFO`, `WARN`, `ERROR`) that can be routed to UART, CAN, or a diagnostic buffer.
## Summary of Priority
| Priority | Improvement | Impact |
| :--- | :--- | :--- |
| **Highest** | Remove `malloc`/`free` | System Stability |
| **High** | Strengthen PEC/Error Checking | Data Integrity |
| **Medium** | Implement DMA | CPU Efficiency |
| **Low** | Replace Magic Numbers | Maintainability |

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# Implementation Plan: Precise Alignment of Forced Balancing with Reference
## 1. Objective
Ensure that the `CanRspForcedBalancingCode` and manual balancing control logic precisely match the reference firmware's behavior and data format, while maintaining support for the 21-cell architecture.
## 2. Requirements
- Align `CanRspForcedBalancingCode` payload with the reference format.
- Support `ManualBalFlag == 2` for direct hardware actuation.
- Handle mode switching (Auto/Manual) exactly as the reference does.
- Maintain documentation in `Revision History.txt`.
## 3. Implementation Steps
### Step 1: Align CAN Response (`can_data_process.c`)
- [ ] Update `CanRspForcedBalancingCode`:
- Process `data->Data[0]` for mode switching.
- Process `data->Data[4]` for potential module balancing (even if currently unused).
- Construct the 8-byte response packet to match the reference:
- Byte 0: `ManualBalFlag`
- Byte 1: `ManualBalEnable` (LSB)
- Byte 2: `ManualBalMode` (LSB)
- Byte 3: 0
- Byte 4: `ManualMdBalMode` (Placeholder)
- Byte 5: `ManualMdBalEnable` (Placeholder)
- Byte 6: `AutoMdBalEnable` (Placeholder)
### Step 2: Refine Manual Control Logic (`ltc6813_comm.c`)
- [ ] Update `SetManualBalancing`:
- Implement logic for `ManualBalFlag == 2` to directly call `MP2642_Enable_Ctrl`.
- Maintain bitmask accumulation for `ManualBalFlag == 1`.
- [ ] Ensure `ManualCellBalancing` correctly handles the `ManualBalFlag` states (0, 1).
### Step 3: Version Update
- [ ] Update `APP_VER_COMPILE` to 4 in `app_ver.c`.
- [ ] Update `BD_MODEL` to "BMU-21S" in `app_ver.h`.
### Step 4: Documentation
- [ ] Update `Revision History.txt`.
## 4. Verification
- [ ] Perform full build.
- [ ] Confirm that CAN responses match the expected reference format.

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# Implementation Plan: CAN Balancing Status Transmission
## 1. Objective
Update the CAN communication logic to transmit the active balancing status of the 21-cell (20-channel) system, ensuring the host can monitor which cells are currently being balanced.
## 2. Requirements
- Report the current active balancing state via `CAN_RSP_BALANCING_CODE` (111).
- Use the `balance_enable` field from `TDEVICE_STATUS` which tracks the actual FET states.
- Maintain compatibility with the reference 8-byte response format.
## 3. Implementation Steps
### Step 1: Logic Update in `can_data_process.c`
- [x] Modify `CanRspBalancingCode` to send `device_status.balance_enable.value`.
- [x] Verify that `balance_enable.value` (32-bit) correctly maps to the 3-byte field (Bytes 4, 5, 6) in the CAN packet, covering all 20 balancing channels.
### Step 2: Documentation
- [x] Update `Revision History.txt` with the CAN reporting change.
## 4. Verification
- [ ] Perform build.
- [ ] (Optional/User) Verify CAN packet data on the host side while balancing is active.

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# Implementation Plan: Fix Build Post-Processing Scripts
## 1. Objective
Correct the post-build scripts (`CopyHex_Flash.bat` and `Hex2Bin_Flash.bat`) to use the latest build output from the `unify_builder` tool and update the output file name to match the new version (V1.0.0.4).
## 2. Requirements
- Ensure `CopyHex_Flash.bat` points to the correct source: `build\BMU_21S_APP\BMU_21S_APP.hex`.
- Update the output file name in both scripts to `BMU_21S_APP_V1004.hex`.
- Maintain synchronization between hex copying and binary generation.
## 3. Implementation Steps
### Step 1: Fix `CopyHex_Flash.bat`
- [x] Change the copy command to: `copy build\BMU_21S_APP\BMU_21S_APP.hex Flash\BMU_21S_APP_V1004.hex`.
### Step 2: Fix `Hex2Bin_Flash.bat`
- [x] Update the conversion command to: `hex2bin.exe -b .\FLASH\BMU_21S_APP_V1004.hex`.
### Step 3: Documentation
- [x] Update `Revision History.txt`.
## 4. Verification
- [ ] Run the build.
- [ ] Verify that `Flash\BMU_21S_APP_V1004.bin` is generated with the current timestamp.

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# Implementation Plan: Porting Forced Balancing and Manual Control
## 1. Objective
Port the manual control (Forced Balancing) logic from the reference firmware to allow explicit control over individual balancing channels and toggle between Auto and Manual balancing modes.
## 2. Requirements
- Implement `CAN_REQ_FORCED_BALANCING_CODE` (12) handling to:
- Toggle `ACB` (Auto Cell Balancing) mode.
- Set specific channels for manual balancing.
- Respond with the current manual control status.
- Update `SetManualBalancing` to process channel-specific commands.
- Update `ManualCellBalancing` to actuate FETs based on manual settings.
## 3. Implementation Steps
### Step 1: CAN Logic Update (`can_data_process.c`)
- [x] Modify `CanRspForcedBalancingCode`:
- If `data->Data[0] == 0`, set `device_status.battery_status.bit.ACB = 1` (Auto Mode).
- If `data->Data[0] == 1`, set `device_status.battery_status.bit.ACB = 0` (Manual Mode).
- Call `SetManualBalancing` with the received data.
- Construct and send `CAN_RSP_FORCED_BALANCING_CODE` (121) with current `ManualBal` flags and values.
### Step 2: Balancing Logic Update (`ltc6813_comm.c`)
- [x] Update `SetManualBalancing(uint8_t flag, uint8_t *data)`:
- Extract `ch`, `mode`, `enable` from `data[1]`, `data[2]`, `data[3]`.
- Update `ManualBalEnable` and `ManualBalMode` bitmasks accordingly.
- [x] Update `ManualCellBalancing`:
- If `ManualBalFlag == 1`, use `ManualBalEnable` to control `MP2642` FETs.
- If `ManualBalFlag == 0`, disable all FETs.
### Step 3: Documentation
- [x] Update `Revision History.txt`.
## 4. Verification
- [ ] Build the project and ensure no errors.
- [ ] Verify mode switching between Auto/Manual via CAN.

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# Implementation Plan: Porting STATUS5 CAN Transmission
## 1. Objective
Port the `CAN_RSP_STATUS5_CODE` (15) transmission logic from the reference firmware to provide the host with visibility into both the desired (`balance_enable`) and actual (`cellbalance`) balancing states.
## 2. Requirements
- Implement `Status #5` response in `CanRspStatusCode`.
- Transmit 8 bytes:
- Bytes 0-3: `device_status.balance_enable.value` (Current Operating Status - 20 bits).
- Bytes 4-7: `device_status.balance_enable.value` (Mirroring current status to ensure visibility in all modes).
- Ensure this value reflects both Auto and Manual balancing states.
## 3. Implementation Steps
### Step 1: Update `CanRspStatusCode` in `can_data_process.c`
- [ ] Add `delay_os_ms(1);` at the end of the current `CanRspStatusCode` function.
- [ ] Implement `Status #5` transmission using `CAN_RSP_STATUS5_CODE`.
- [ ] Map `balance_enable.value` and `cellbalance.value` to the 8-byte packet as specified.
### Step 2: Documentation
- [ ] Update `Revision History.txt`.
## 4. Verification
- [ ] Build the project and ensure no errors.
- [ ] Verify that 5 status messages (ID 211, 212, 213, 214, 215) are transmitted in sequence when requested.

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# Implementation Plan: Module Balancing Removal and Warning Fix
## 1. Objective
Remove the "Module Balancing" feature as it is not required for this project, and resolve compilation warnings identified in the latest build.
## 2. Requirements
- Remove all code related to `ManualMdBalEnable`, `ManualMdBalMode`, and `SetManualBalancingMd`.
- Fix implicit declaration warnings for `MP2642_Enable_Ctrl` and `MP2642_EnaDis_All`.
- Clean up unused variables to ensure a warning-free build.
## 3. Implementation Steps
### Step 1: Interface Cleanup
- [x] Remove `SetManualBalancingMd` prototype from `ltc6813_comm.h`.
### Step 2: Implementation Cleanup and Fixes
- [x] Remove `ManualMdBalEnable` and `ManualMdBalMode` from `ltc6813_comm.c`.
- [x] Remove `SetManualBalancingMd` implementation from `ltc6813_comm.c`.
- [x] Add `#include "io.h"` to `ltc6813_comm.c` to provide prototypes for `MP2642` control functions.
- [x] Remove unused `error` variable in `ReadCellVoltage` function in `ltc6813_comm.c`.
### Step 3: Documentation
- [x] Update `Revision History.txt`.
## 4. Verification
- [ ] Perform build and confirm 0 errors and 0 warnings (related to the changes).

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# Project Analysis: BMU 21S Application
## 1. Project Overview
This project is a firmware implementation for a **Battery Management Unit (BMU)**, specifically designed for a 21S (21 cells in series) configuration. It is built on an **STM32F10x** microcontroller platform and utilizes the **$\mu$C/OS-III** Real-Time Operating System (RTOS).
## 2. System Architecture
### 2.1 Hardware Abstraction & Drivers
- **MCU:** STM32F10x (Cortex-M3).
- **Communication Interfaces:**
- **CAN Bus:** Used for high-level communication (likely with a host controller).
- **SPI:** Used for communicating with battery monitoring ICs (LTC6813).
- **UART/Console:** Used for debugging and user interface.
- **Peripheral Drivers:** Standard STM32 peripheral drivers (`FWLIB`) are used for GPIO, SPI, CAN, etc.
### 2.2 Software Layers
- **Application Layer (`APP/`):** Contains the core business logic, including battery management, CAN communication, and task management.
- **Middleware/OS Layer (`UCOSIII/`):** $\mu$C/OS-III provides task scheduling, semaphores, mutexes, and message queues.
- **Hardware Abstraction Layer (`HARDWARE/`, `SYSTEM/`):** Provides low-level drivers for SPI, CAN, IWDG, LED, and system utilities (delay, usart).
- **Library Layer (`FWLIB/`):** STM32 Standard Peripheral Library.
## 3. Core Functional Modules
### 3.1 Battery Management (`APP/battery_comm.c`)
- **LTC6813 Interface:** Implements SPI communication to interact with LTC6813 battery monitoring ICs.
- **Cell Voltage Monitoring:** Functions like `request_battery_voltage_A/B/C/D` allow reading voltages from different cell groups.
- **Configuration:** Supports reading and writing configuration registers to the LTC6813 daisy chain.
- **Daisy Chain Support:** Handles multiple ICs connected in a daisy chain via SPI.
### 3.2 CAN Communication (`APP/can_comm.c`)
- **Task-Based:** Runs in a dedicated `can_comm_task`.
- **Packet Processing:**
- **Firmware Update:** Handles incoming packets for F/W updates (`FwUpdateProcess`).
- **Normal Communication:** Processes standard data packets (`CanRxDataProcess`).
- **Inventory Data:** Processes inventory-related packets (`CanRxInvDataProcess`).
- **Reliability:** Includes timeout checks (`CanCommFailCheck`) and error handling for the CAN peripheral.
### 3.3 Task Management & OS Integration
The system is highly multi-tasked, with tasks running at different priorities:
| Task Name | Priority | Description |
| :--- | :--- | :--- |
| `BATT task` | 3 | Battery monitoring and LTC6813 communication. |
| `CAN Comm Task` | 4 | CAN bus communication and packet processing. |
| `Temp task` | 5 | Temperature monitoring. |
| `IO task` | 6 | General I/O operations. |
| `Start Task` | 7 | Initialization and task creation. |
`APP/task_manager.c` manages Task Control Blocks (TCB) and provides debugging utilities to monitor task CPU usage and stack status.
## 4. Project Structure Summary
- `APP/`: High-level application logic.
- `CORE/`: Core startup and processor-specific code.
- `DOC/`: Documentation and analysis reports.
- `FWLIB/`: STM32 peripheral drivers.
- `HARDWARE/`: Low-level hardware drivers (SPI, CAN, etc.).
- `SYSTEM/`: System-level utilities (Delay, USART).
- `UCOSIII/`: $\mu$C/OS-III RTOS source and configuration.
- `USER/`: Main entry point (`main.c`), project configuration (Keil), and build artifacts.
## 5. Key Observations
- **Safety-Critical Design:** Use of an RTOS, watchdog (IWDG), and PEC (Packet Error Code) for SPI/CAN indicates a focus on reliability and safety.
- **Modular Design:** Clear separation between hardware drivers, OS, and application logic.
- **Daisy Chain Support:** Specifically designed to handle multiple battery monitoring chips in a sequence.

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<!--
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{mso-style-parent:"";
margin:0in;
margin-bottom:.0001pt;
mso-pagination:widow-orphan;
font-size:12.0pt;
font-family:"Times New Roman";
mso-fareast-font-family:"Times New Roman";}
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{mso-style-next:Normal;
margin-top:12.0pt;
margin-right:0in;
margin-bottom:3.0pt;
margin-left:0in;
mso-pagination:widow-orphan;
page-break-after:avoid;
mso-outline-level:2;
font-size:14.0pt;
font-family:Arial;
font-weight:bold;
font-style:italic;}
a:link, span.MsoHyperlink
{color:blue;
text-decoration:underline;
text-underline:single;}
a:visited, span.MsoHyperlinkFollowed
{color:blue;
text-decoration:underline;
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{mso-margin-top-alt:auto;
margin-right:0in;
mso-margin-bottom-alt:auto;
margin-left:0in;
mso-pagination:widow-orphan;
font-size:12.0pt;
font-family:"Times New Roman";
mso-fareast-font-family:"Times New Roman";}
@page Section1
{size:8.5in 11.0in;
margin:1.0in 1.25in 1.0in 1.25in;
mso-header-margin:.5in;
mso-footer-margin:.5in;
mso-paper-source:0;}
div.Section1
{page:Section1;}
-->
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<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
Notes for STM32F10x Standard Peripherals Library Drivers
(StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
<ol style="margin-top: 0cm;" start="1" type="1">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library
Drivers update History</a><o:p></o:p></span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
</ol>
<span style="font-family: &quot;Times New Roman&quot;;">
</span>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard
Peripherals Library Drivers&nbsp; update History</span></h2><br>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c files:</span></li>
<ul>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 5 new functions</span></li>
<ul>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">3
new functions controlling the counter errors: CAN_GetLastErrorCode(),
CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().</span></li>
</ul>
<ul>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">1 new function to select the CAN operating mode: CAN_OperatingModeRequest().</span></li>
</ul>
<ul>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">1 new function to support CAN TT mode: CAN_TTComModeCmd().</span><span style="font-size: 10pt; font-family: Verdana;"><br>
</span></li>
</ul>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN_TransmitStatus() function updated to support all CAN transmit intermediate states<br>
</span></li>
</ul>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c files:</span></li>
<ul>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 1 new function:</span></li>
<ul>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C_NACKPositionConfig():
This function configures the same bit (POS) as I2C_PECPositionConfig()
but is intended to be used in I2C mode while I2C_PECPositionConfig() is
intended to used in SMBUS mode.</span></li>
</ul>
</ul>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c files:</span></li>
<ul>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the <span style="font-style: italic;">TIM_DMABurstLength_xBytes</span> definitions to <span style="font-style: italic;">TIM_DMABurstLength_xTansfers</span><br>
</span></li>
</ul>
</ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
- 10/15/2010</span></h3>
<ol style="margin-top: 0in;" start="1" type="1">
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
</ol>
<ul style="margin-top: 0in;" type="disc">
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x High-density value line </span>devices.</span></li>
</ul>
<ol style="margin-top: 0in;" start="2" type="1">
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
</ol>
<ul style="margin-top: 0in;" type="disc">
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_bkp.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file. </span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.<br>
</span></span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Update the wording of some defines and Asserts macro. <br>
</span></span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetFlagStatus()
and CAN_ClearFlag() functions: updated to support new flags (were not
supported in previous version). These flags are:&nbsp; CAN_FLAG_RQCP0,
CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1,
CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0,&nbsp;&nbsp; CAN_FLAG_FOV0,
CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC. <br>
</span></span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetITStatus()
function: add a check of the interrupt enable bit before getting the
status of corresponding interrupt pending bit. <br>
</span></span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit. <br>
</span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_crc.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.</span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dac.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file. </span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file. </span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dma.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.</span></span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"<br>
</span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.</span><span style="font-style: italic;"></span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_fsmc.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.</span><span style="font-style: italic;"></span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.</span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_pwr.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.</span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rtc.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.</span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_spi.h/.c</span></li>
<ul>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".</span></span></li>
</ul>
<li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c</span></li>
<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".</span></span></li></ul>
</ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
- 04/16/2010</span></h3>
<ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>
<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density </span>devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C driver: events description and management enhancement.</span></li></ul>
<ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">DBGMCU_Config()</span> function: add new values <span style="font-style: italic;">DBGMCU_TIMx_STOP</span> (x: 9..14) for <span style="font-style: italic;">DBGMCU_Periph</span> parameter.</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c:
updated to support Bank2 of XL-density devices (up to 1MByte of Flash
memory). For more details, refer to the description provided within
stm32f10x_flash.c file.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for FSMC_NADV pin and TIM9..11,13,14.</span></span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c: I2C events description and management enhancement. <br></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">I2C_CheckEvent()</span>
function: updated to check whether the last event contains the
I2C_EVENT&nbsp; (instead of check whether the last event is equal to
I2C_EVENT)<br></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add
detailed description of I2C events and how to manage them using the
functions provided by this driver. For more information, refer to
stm32f10x_i2c.h and stm32f10x_i2c.c files.</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_sdio.h:&nbsp;</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter<br>change <br>&nbsp;
#define
SDIO_ReadWaitMode_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&nbsp; ((uint32_t)0x00000000)<br>&nbsp; #define
SDIO_ReadWaitMode_DATA2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
((uint32_t)0x00000001)<br>by<br>&nbsp; #define
SDIO_ReadWaitMode_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&nbsp; ((uint32_t)0x00000001)<br>&nbsp; #define
SDIO_ReadWaitMode_DATA2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
((uint32_t)0x00000000)</span></li></ul></ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
- 03/01/2010</span></h3>
<ol style="margin-top: 0in;" start="1" type="1">
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
</ol>
<ul style="margin-top: 0in;" type="disc">
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and
Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Almost
peripherals drivers were updated to support Value
line devices features</span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Drivers limitations fix and enhancements. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>
</ul>
<ol style="margin-top: 0in;" start="2" type="1">
<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
</ol>
<ul style="margin-top: 0in;" type="disc">
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new
firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c</span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.</span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.</span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM1_DMA, </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.</span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">USART
driver: add support for Oversampling by 8 mode and onebit method. 2
functions has been added: USART_OverSampling8Cmd() and
USART_OneBitMethodCmd().<br>
</span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DAC
driver: add new functions handling the DAC under run feature:
DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus()
and DAC_ClearITPendingBit().</span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.<br>
</span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">FLASH
driver: the FLASH_EraseOptionBytes() function updated. This is now just
erasing the option bytes without modifying the RDP status either
enabled or disabled.</span></li>
<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">PWR
driver: the PWR_EnterSTOPMode() function updated. When woken up from
STOP mode, this function resets again the SLEEPDEEP bit in the
Cortex-M3 System Control register to allow Sleep mode entering.</span></li>
</ul>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
enclosed firmware and all the related documentation are not covered by
a License Agreement, if you need such License you can contact your
local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
THEIR PRODUCTS. <o:p></o:p></span></b></p>
<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
<hr align="center" size="2" width="100%"></span></div>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
</td>
</tr>
</tbody>
</table>
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
</td>
</tr>
</tbody>
</table>
</div>
<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
</div>
</body></html>

220
FWLIB/STM32F10x_StdPeriph_Driver/inc/misc.h Normal file
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/**
******************************************************************************
* @file misc.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MISC_H
#define __MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @defgroup MISC_Exported_Types
* @{
*/
/**
* @brief NVIC Init Structure definition
*/
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete STM32 Devices IRQ Channels list, please
refer to stm32f10x.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitTypeDef;
/**
* @}
*/
/** @defgroup NVIC_Priority_Table
* @{
*/
/**
@code
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority
============================================================================================================================
@endcode
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Constants
* @{
*/
/** @defgroup Vector_Table_Base
* @{
*/
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @defgroup System_Low_Power
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @defgroup Preemption_Priority_Group
* @{
*/
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/**
* @}
*/
/** @defgroup SysTick_clock_source
* @{
*/
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/**
* @}
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Functions
* @{
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#ifdef __cplusplus
}
#endif
#endif /* __MISC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

483
FWLIB/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h Normal file
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/**
******************************************************************************
* @file stm32f10x_adc.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_ADC_H
#define __STM32F10x_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/** @defgroup ADC_Exported_Types
* @{
*/
/**
* @brief ADC Init structure definition
*/
typedef struct
{
uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
dual mode.
This parameter can be a value of @ref ADC_mode */
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align */
uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
using the sequencer for regular channel group.
This parameter must range from 1 to 16. */
}ADC_InitTypeDef;
/**
* @}
*/
/** @defgroup ADC_Exported_Constants
* @{
*/
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
((PERIPH) == ADC2) || \
((PERIPH) == ADC3))
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
((PERIPH) == ADC3))
/** @defgroup ADC_mode
* @{
*/
#define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
((MODE) == ADC_Mode_RegInjecSimult) || \
((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
((MODE) == ADC_Mode_InjecSimult) || \
((MODE) == ADC_Mode_RegSimult) || \
((MODE) == ADC_Mode_FastInterl) || \
((MODE) == ADC_Mode_SlowInterl) || \
((MODE) == ADC_Mode_AlterTrig))
/**
* @}
*/
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_None) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
/**
* @}
*/
/** @defgroup ADC_data_align
* @{
*/
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
((ALIGN) == ADC_DataAlign_Left))
/**
* @}
*/
/** @defgroup ADC_channels
* @{
*/
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
#define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
/**
* @}
*/
/** @defgroup ADC_sampling_time
* @{
*/
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
((TIME) == ADC_SampleTime_7Cycles5) || \
((TIME) == ADC_SampleTime_13Cycles5) || \
((TIME) == ADC_SampleTime_28Cycles5) || \
((TIME) == ADC_SampleTime_41Cycles5) || \
((TIME) == ADC_SampleTime_55Cycles5) || \
((TIME) == ADC_SampleTime_71Cycles5) || \
((TIME) == ADC_SampleTime_239Cycles5))
/**
* @}
*/
/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
/**
* @}
*/
/** @defgroup ADC_injected_channel_selection
* @{
*/
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
((CHANNEL) == ADC_InjectedChannel_2) || \
((CHANNEL) == ADC_InjectedChannel_3) || \
((CHANNEL) == ADC_InjectedChannel_4))
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_selection
* @{
*/
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_None))
/**
* @}
*/
/** @defgroup ADC_interrupts_definition
* @{
*/
#define ADC_IT_EOC ((uint16_t)0x0220)
#define ADC_IT_AWD ((uint16_t)0x0140)
#define ADC_IT_JEOC ((uint16_t)0x0480)
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
((IT) == ADC_IT_JEOC))
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @{
*/
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10)
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
((FLAG) == ADC_FLAG_STRT))
/**
* @}
*/
/** @defgroup ADC_thresholds
* @{
*/
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_offset
* @{
*/
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_length
* @{
*/
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_injected_rank
* @{
*/
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_regular_length
* @{
*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_rank
* @{
*/
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_discontinuous_mode_number
* @{
*/
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
/**
* @}
*/
/**
* @}
*/
/** @defgroup ADC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup ADC_Exported_Functions
* @{
*/
void ADC_DeInit(ADC_TypeDef* ADCx);
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_StartCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
uint32_t ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_ADC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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FWLIB/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h Normal file
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@@ -0,0 +1,195 @@
/**
******************************************************************************
* @file stm32f10x_bkp.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the BKP firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_BKP_H
#define __STM32F10x_BKP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup BKP
* @{
*/
/** @defgroup BKP_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Constants
* @{
*/
/** @defgroup Tamper_Pin_active_level
* @{
*/
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
((LEVEL) == BKP_TamperPinLevel_Low))
/**
* @}
*/
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
* @{
*/
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
((SOURCE) == BKP_RTCOutputSource_Alarm) || \
((SOURCE) == BKP_RTCOutputSource_Second))
/**
* @}
*/
/** @defgroup Data_Backup_Register
* @{
*/
#define BKP_DR1 ((uint16_t)0x0004)
#define BKP_DR2 ((uint16_t)0x0008)
#define BKP_DR3 ((uint16_t)0x000C)
#define BKP_DR4 ((uint16_t)0x0010)
#define BKP_DR5 ((uint16_t)0x0014)
#define BKP_DR6 ((uint16_t)0x0018)
#define BKP_DR7 ((uint16_t)0x001C)
#define BKP_DR8 ((uint16_t)0x0020)
#define BKP_DR9 ((uint16_t)0x0024)
#define BKP_DR10 ((uint16_t)0x0028)
#define BKP_DR11 ((uint16_t)0x0040)
#define BKP_DR12 ((uint16_t)0x0044)
#define BKP_DR13 ((uint16_t)0x0048)
#define BKP_DR14 ((uint16_t)0x004C)
#define BKP_DR15 ((uint16_t)0x0050)
#define BKP_DR16 ((uint16_t)0x0054)
#define BKP_DR17 ((uint16_t)0x0058)
#define BKP_DR18 ((uint16_t)0x005C)
#define BKP_DR19 ((uint16_t)0x0060)
#define BKP_DR20 ((uint16_t)0x0064)
#define BKP_DR21 ((uint16_t)0x0068)
#define BKP_DR22 ((uint16_t)0x006C)
#define BKP_DR23 ((uint16_t)0x0070)
#define BKP_DR24 ((uint16_t)0x0074)
#define BKP_DR25 ((uint16_t)0x0078)
#define BKP_DR26 ((uint16_t)0x007C)
#define BKP_DR27 ((uint16_t)0x0080)
#define BKP_DR28 ((uint16_t)0x0084)
#define BKP_DR29 ((uint16_t)0x0088)
#define BKP_DR30 ((uint16_t)0x008C)
#define BKP_DR31 ((uint16_t)0x0090)
#define BKP_DR32 ((uint16_t)0x0094)
#define BKP_DR33 ((uint16_t)0x0098)
#define BKP_DR34 ((uint16_t)0x009C)
#define BKP_DR35 ((uint16_t)0x00A0)
#define BKP_DR36 ((uint16_t)0x00A4)
#define BKP_DR37 ((uint16_t)0x00A8)
#define BKP_DR38 ((uint16_t)0x00AC)
#define BKP_DR39 ((uint16_t)0x00B0)
#define BKP_DR40 ((uint16_t)0x00B4)
#define BKP_DR41 ((uint16_t)0x00B8)
#define BKP_DR42 ((uint16_t)0x00BC)
#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
/**
* @}
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Functions
* @{
*/
void BKP_DeInit(void);
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
void BKP_TamperPinCmd(FunctionalState NewState);
void BKP_ITConfig(FunctionalState NewState);
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
FlagStatus BKP_GetFlagStatus(void);
void BKP_ClearFlag(void);
ITStatus BKP_GetITStatus(void);
void BKP_ClearITPendingBit(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_BKP_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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FWLIB/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h Normal file
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/**
******************************************************************************
* @file stm32f10x_can.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the CAN firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CAN_H
#define __STM32F10x_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup CAN
* @{
*/
/** @defgroup CAN_Exported_Types
* @{
*/
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
((PERIPH) == CAN2))
/**
* @brief CAN init structure definition
*/
typedef struct
{
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
It ranges from 1 to 1024. */
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of
@ref CAN_operating_mode */
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of
@ref CAN_synchronisation_jump_width */
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
Segment 1. This parameter can be a value of
@ref CAN_time_quantum_in_bit_segment_1 */
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit
Segment 2.
This parameter can be a value of
@ref CAN_time_quantum_in_bit_segment_2 */
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
communication mode. This parameter can be set
either to ENABLE or DISABLE. */
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off
management. This parameter can be set either
to ENABLE or DISABLE. */
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set either to ENABLE or
DISABLE. */
FunctionalState CAN_NART; /*!< Enable or disable the no-automatic
retransmission mode. This parameter can be
set either to ENABLE or DISABLE. */
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
This parameter can be set either to ENABLE
or DISABLE. */
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
This parameter can be set either to ENABLE
or DISABLE. */
} CAN_InitTypeDef;
/**
* @brief CAN filter init structure definition
*/
typedef struct
{
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
This parameter can be set either to ENABLE or DISABLE. */
} CAN_FilterInitTypeDef;
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /*!< Specifies the type of identifier for the message that
will be transmitted. This parameter can be a value
of @ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the message that will
be transmitted. This parameter can be a value of
@ref CAN_remote_transmission_request */
uint8_t DLC; /*!< Specifies the length of the frame that will be
transmitted. This parameter can be a value between
0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
to 0xFF. */
} CanTxMsg;
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /*!< Specifies the type of identifier for the message that
will be received. This parameter can be a value of
@ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of
@ref CAN_remote_transmission_request */
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter can be a value between 0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
0xFF. */
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
the mailbox passes through. This parameter can be a
value between 0 to 0xFF */
} CanRxMsg;
/**
* @}
*/
/** @defgroup CAN_Exported_Constants
* @{
*/
/** @defgroup CAN_sleep_constants
* @{
*/
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
/**
* @}
*/
/** @defgroup CAN_Mode
* @{
*/
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
((MODE) == CAN_Mode_LoopBack)|| \
((MODE) == CAN_Mode_Silent) || \
((MODE) == CAN_Mode_Silent_LoopBack))
/**
* @}
*/
/**
* @defgroup CAN_Operating_Mode
* @{
*/
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
((MODE) == CAN_OperatingMode_Normal)|| \
((MODE) == CAN_OperatingMode_Sleep))
/**
* @}
*/
/**
* @defgroup CAN_Mode_Status
* @{
*/
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
/**
* @}
*/
/** @defgroup CAN_synchronisation_jump_width
* @{
*/
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_1
* @{
*/
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_2
* @{
*/
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
/**
* @}
*/
/** @defgroup CAN_clock_prescaler
* @{
*/
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
/**
* @}
*/
/** @defgroup CAN_filter_number
* @{
*/
#ifndef STM32F10X_CL
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
#else
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
#endif /* STM32F10X_CL */
/**
* @}
*/
/** @defgroup CAN_filter_mode
* @{
*/
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
((MODE) == CAN_FilterMode_IdList))
/**
* @}
*/
/** @defgroup CAN_filter_scale
* @{
*/
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
((SCALE) == CAN_FilterScale_32bit))
/**
* @}
*/
/** @defgroup CAN_filter_FIFO
* @{
*/
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
((FIFO) == CAN_FilterFIFO1))
/**
* @}
*/
/** @defgroup Start_bank_filter_for_slave_CAN
* @{
*/
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
/**
* @}
*/
/** @defgroup CAN_Tx
* @{
*/
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
/**
* @}
*/
/** @defgroup CAN_identifier_type
* @{
*/
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
((IDTYPE) == CAN_Id_Extended))
/**
* @}
*/
/** @defgroup CAN_remote_transmission_request
* @{
*/
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
/**
* @}
*/
/** @defgroup CAN_transmit_constants
* @{
*/
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
/**
* @}
*/
/** @defgroup CAN_receive_FIFO_number_constants
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
/**
* @}
*/
/** @defgroup CAN_sleep_constants
* @{
*/
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
/**
* @}
*/
/** @defgroup CAN_wake_up_constants
* @{
*/
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
/**
* @}
*/
/**
* @defgroup CAN_Error_Code_constants
* @{
*/
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
/**
* @}
*/
/** @defgroup CAN_flags
* @{
*/
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
and CAN_ClearFlag() functions. */
/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
/* Receive Flags */
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
/* Operating Mode Flags */
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
((FLAG) == CAN_FLAG_SLAK ))
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
/**
* @}
*/
/** @defgroup CAN_interrupts
* @{
*/
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
/* Flags named as Interrupts : kept only for FW compatibility */
#define CAN_IT_RQCP0 CAN_IT_TME
#define CAN_IT_RQCP1 CAN_IT_TME
#define CAN_IT_RQCP2 CAN_IT_TME
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/**
* @}
*/
/** @defgroup CAN_Legacy
* @{
*/
#define CANINITFAILED CAN_InitStatus_Failed
#define CANINITOK CAN_InitStatus_Success
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
#define CAN_ID_STD CAN_Id_Standard
#define CAN_ID_EXT CAN_Id_Extended
#define CAN_RTR_DATA CAN_RTR_Data
#define CAN_RTR_REMOTE CAN_RTR_Remote
#define CANTXFAILE CAN_TxStatus_Failed
#define CANTXOK CAN_TxStatus_Ok
#define CANTXPENDING CAN_TxStatus_Pending
#define CAN_NO_MB CAN_TxStatus_NoMailBox
#define CANSLEEPFAILED CAN_Sleep_Failed
#define CANSLEEPOK CAN_Sleep_Ok
#define CANWAKEUPFAILED CAN_WakeUp_Failed
#define CANWAKEUPOK CAN_WakeUp_Ok
/**
* @}
*/
/**
* @}
*/
/** @defgroup CAN_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CAN_Exported_Functions
* @{
*/
/* Function used to set the CAN configuration to the default reset state *****/
void CAN_DeInit(CAN_TypeDef* CANx);
/* Initialization and Configuration functions *********************************/
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
/* Transmit functions *********************************************************/
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
/* Receive functions **********************************************************/
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
/* Operation modes functions **************************************************/
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
/* Error management functions *************************************************/
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
/* Interrupts and flags management functions **********************************/
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_CAN_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_cec.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the CEC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CEC_H
#define __STM32F10x_CEC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup CEC
* @{
*/
/** @defgroup CEC_Exported_Types
* @{
*/
/**
* @brief CEC Init structure definition
*/
typedef struct
{
uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
This parameter can be a value of @ref CEC_BitTiming_Mode */
uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
This parameter can be a value of @ref CEC_BitPeriod_Mode */
}CEC_InitTypeDef;
/**
* @}
*/
/** @defgroup CEC_Exported_Constants
* @{
*/
/** @defgroup CEC_BitTiming_Mode
* @{
*/
#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
((MODE) == CEC_BitTimingErrFreeMode))
/**
* @}
*/
/** @defgroup CEC_BitPeriod_Mode
* @{
*/
#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
((MODE) == CEC_BitPeriodFlexibleMode))
/**
* @}
*/
/** @defgroup CEC_interrupts_definition
* @{
*/
#define CEC_IT_TERR CEC_CSR_TERR
#define CEC_IT_TBTRF CEC_CSR_TBTRF
#define CEC_IT_RERR CEC_CSR_RERR
#define CEC_IT_RBTF CEC_CSR_RBTF
#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
/**
* @}
*/
/** @defgroup CEC_Own_Address
* @{
*/
#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
/**
* @}
*/
/** @defgroup CEC_Prescaler
* @{
*/
#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
/**
* @}
*/
/** @defgroup CEC_flags_definition
* @{
*/
/**
* @brief ESR register flags
*/
#define CEC_FLAG_BTE ((uint32_t)0x10010000)
#define CEC_FLAG_BPE ((uint32_t)0x10020000)
#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
#define CEC_FLAG_SBE ((uint32_t)0x10080000)
#define CEC_FLAG_ACKE ((uint32_t)0x10100000)
#define CEC_FLAG_LINE ((uint32_t)0x10200000)
#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
/**
* @brief CSR register flags
*/
#define CEC_FLAG_TEOM ((uint32_t)0x00000002)
#define CEC_FLAG_TERR ((uint32_t)0x00000004)
#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
#define CEC_FLAG_RSOM ((uint32_t)0x00000010)
#define CEC_FLAG_REOM ((uint32_t)0x00000020)
#define CEC_FLAG_RERR ((uint32_t)0x00000040)
#define CEC_FLAG_RBTF ((uint32_t)0x00000080)
#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
/**
* @}
*/
/**
* @}
*/
/** @defgroup CEC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CEC_Exported_Functions
* @{
*/
void CEC_DeInit(void);
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
void CEC_Cmd(FunctionalState NewState);
void CEC_ITConfig(FunctionalState NewState);
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
void CEC_SetPrescaler(uint16_t CEC_Prescaler);
void CEC_SendDataByte(uint8_t Data);
uint8_t CEC_ReceiveDataByte(void);
void CEC_StartOfMessage(void);
void CEC_EndOfMessageCmd(FunctionalState NewState);
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
void CEC_ClearFlag(uint32_t CEC_FLAG);
ITStatus CEC_GetITStatus(uint8_t CEC_IT);
void CEC_ClearITPendingBit(uint16_t CEC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_CEC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_crc.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_CRC_H
#define __STM32F10x_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Constants
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Exported_Functions
* @{
*/
void CRC_ResetDR(void);
uint32_t CRC_CalcCRC(uint32_t Data);
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC_GetCRC(void);
void CRC_SetIDRegister(uint8_t IDValue);
uint8_t CRC_GetIDRegister(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_CRC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_dac.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DAC_H
#define __STM32F10x_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/** @defgroup DAC_Exported_Types
* @{
*/
/**
* @brief DAC Init structure definition
*/
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_InitTypeDef;
/**
* @}
*/
/** @defgroup DAC_Exported_Constants
* @{
*/
/** @defgroup DAC_trigger_selection
* @{
*/
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
only in High-density devices*/
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
only in Connectivity line, Medium-density and Low-density Value Line devices */
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
only in Medium-density and Low-density Value Line devices*/
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
((TRIGGER) == DAC_Trigger_Software))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
((WAVE) == DAC_WaveGeneration_Noise) || \
((WAVE) == DAC_WaveGeneration_Triangle))
/**
* @}
*/
/** @defgroup DAC_lfsrunmask_triangleamplitude
* @{
*/
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
((VALUE) == DAC_TriangleAmplitude_1) || \
((VALUE) == DAC_TriangleAmplitude_3) || \
((VALUE) == DAC_TriangleAmplitude_7) || \
((VALUE) == DAC_TriangleAmplitude_15) || \
((VALUE) == DAC_TriangleAmplitude_31) || \
((VALUE) == DAC_TriangleAmplitude_63) || \
((VALUE) == DAC_TriangleAmplitude_127) || \
((VALUE) == DAC_TriangleAmplitude_255) || \
((VALUE) == DAC_TriangleAmplitude_511) || \
((VALUE) == DAC_TriangleAmplitude_1023) || \
((VALUE) == DAC_TriangleAmplitude_2047) || \
((VALUE) == DAC_TriangleAmplitude_4095))
/**
* @}
*/
/** @defgroup DAC_output_buffer
* @{
*/
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
((STATE) == DAC_OutputBuffer_Disable))
/**
* @}
*/
/** @defgroup DAC_Channel_selection
* @{
*/
#define DAC_Channel_1 ((uint32_t)0x00000000)
#define DAC_Channel_2 ((uint32_t)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
/**
* @}
*/
/** @defgroup DAC_data_alignment
* @{
*/
#define DAC_Align_12b_R ((uint32_t)0x00000000)
#define DAC_Align_12b_L ((uint32_t)0x00000004)
#define DAC_Align_8b_R ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
((ALIGN) == DAC_Align_12b_L) || \
((ALIGN) == DAC_Align_8b_R))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_Wave_Noise ((uint32_t)0x00000040)
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
/**
* @}
*/
/** @defgroup DAC_data
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/** @defgroup DAC_interrupts_definition
* @{
*/
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
/**
* @}
*/
/** @defgroup DAC_flags_definition
* @{
*/
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
/**
* @}
*/
#endif
/**
* @}
*/
/** @defgroup DAC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Exported_Functions
* @{
*/
void DAC_DeInit(void);
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
#endif
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
#endif
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_DAC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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FWLIB/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h Normal file
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/**
******************************************************************************
* @file stm32f10x_dbgmcu.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the DBGMCU
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DBGMCU_H
#define __STM32F10x_DBGMCU_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup DBGMCU
* @{
*/
/** @defgroup DBGMCU_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Constants
* @{
*/
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_STOP ((uint32_t)0x00000002)
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Exported_Functions
* @{
*/
uint32_t DBGMCU_GetREVID(void);
uint32_t DBGMCU_GetDEVID(void);
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_DBGMCU_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_dma.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_DMA_H
#define __STM32F10x_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_Exported_Types
* @{
*/
/**
* @brief DMA Init structure definition
*/
typedef struct
{
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
}DMA_InitTypeDef;
/**
* @}
*/
/** @defgroup DMA_Exported_Constants
* @{
*/
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
((PERIPH) == DMA1_Channel2) || \
((PERIPH) == DMA1_Channel3) || \
((PERIPH) == DMA1_Channel4) || \
((PERIPH) == DMA1_Channel5) || \
((PERIPH) == DMA1_Channel6) || \
((PERIPH) == DMA1_Channel7) || \
((PERIPH) == DMA2_Channel1) || \
((PERIPH) == DMA2_Channel2) || \
((PERIPH) == DMA2_Channel3) || \
((PERIPH) == DMA2_Channel4) || \
((PERIPH) == DMA2_Channel5))
/** @defgroup DMA_data_transfer_direction
* @{
*/
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
((DIR) == DMA_DIR_PeripheralSRC))
/**
* @}
*/
/** @defgroup DMA_peripheral_incremented_mode
* @{
*/
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
((STATE) == DMA_PeripheralInc_Disable))
/**
* @}
*/
/** @defgroup DMA_memory_incremented_mode
* @{
*/
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
((STATE) == DMA_MemoryInc_Disable))
/**
* @}
*/
/** @defgroup DMA_peripheral_data_size
* @{
*/
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
((SIZE) == DMA_PeripheralDataSize_Word))
/**
* @}
*/
/** @defgroup DMA_memory_data_size
* @{
*/
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
((SIZE) == DMA_MemoryDataSize_Word))
/**
* @}
*/
/** @defgroup DMA_circular_normal_mode
* @{
*/
#define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000)
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
/**
* @}
*/
/** @defgroup DMA_priority_level
* @{
*/
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000)
#define DMA_Priority_Low ((uint32_t)0x00000000)
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
((PRIORITY) == DMA_Priority_High) || \
((PRIORITY) == DMA_Priority_Medium) || \
((PRIORITY) == DMA_Priority_Low))
/**
* @}
*/
/** @defgroup DMA_memory_to_memory
* @{
*/
#define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000)
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
/**
* @}
*/
/** @defgroup DMA_interrupts_definition
* @{
*/
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008)
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @{
*/
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
/**
* @}
*/
/** @defgroup DMA_Buffer_Size
* @{
*/
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
/**
* @}
*/
/**
* @}
*/
/** @defgroup DMA_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Exported_Functions
* @{
*/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
void DMA_ClearFlag(uint32_t DMAy_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_DMA_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_exti.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_EXTI_H
#define __STM32F10x_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** @defgroup EXTI_Exported_Types
* @{
*/
/**
* @brief EXTI mode enumeration
*/
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
}EXTIMode_TypeDef;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
}EXTITrigger_TypeDef;
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling))
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
}EXTI_InitTypeDef;
/**
* @}
*/
/** @defgroup EXTI_Exported_Constants
* @{
*/
/** @defgroup EXTI_Lines
* @{
*/
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
Wakeup from suspend event */
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
/**
* @}
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions
* @{
*/
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_EXTI_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_flash.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FLASH_H
#define __STM32F10x_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @defgroup FLASH_Exported_Types
* @{
*/
/**
* @brief FLASH Status
*/
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
/**
* @}
*/
/** @defgroup FLASH_Exported_Constants
* @{
*/
/** @defgroup Flash_Latency
* @{
*/
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2))
/**
* @}
*/
/** @defgroup Half_Cycle_Enable_Disable
* @{
*/
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
((STATE) == FLASH_HalfCycleAccess_Disable))
/**
* @}
*/
/** @defgroup Prefetch_Buffer_Enable_Disable
* @{
*/
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
((STATE) == FLASH_PrefetchBuffer_Disable))
/**
* @}
*/
/** @defgroup Option_Bytes_Write_Protection
* @{
*/
/* Values to be used with STM32 Low and Medium density devices */
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
/* Values to be used with STM32 Medium-density devices */
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 0 to 1 */
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 2 to 3 */
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 4 to 5 */
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 6 to 7 */
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 8 to 9 */
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 10 to 11 */
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 12 to 13 */
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 14 to 15 */
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 16 to 17 */
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 18 to 19 */
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 20 to 21 */
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 22 to 23 */
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 24 to 25 */
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 26 to 27 */
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 28 to 29 */
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 30 to 31 */
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 32 to 33 */
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 34 to 35 */
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 36 to 37 */
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 38 to 39 */
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 40 to 41 */
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 42 to 43 */
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 44 to 45 */
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 46 to 47 */
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 48 to 49 */
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 50 to 51 */
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 52 to 53 */
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 54 to 55 */
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 56 to 57 */
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 58 to 59 */
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
Write protection of page 60 to 61 */
#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
/**
* @}
*/
/** @defgroup Option_Bytes_IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STOP
* @{
*/
#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STDBY
* @{
*/
#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
#ifdef STM32F10X_XL
/**
* @}
*/
/** @defgroup FLASH_Boot
* @{
*/
#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank1(Default) */
#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank 2 or Bank 1,
depending on the activation of the bank */
#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
#endif
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
*/
#ifdef STM32F10X_XL
#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */
#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
#else
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
#endif
/**
* @}
*/
/** @defgroup FLASH_Flags
* @{
*/
#ifdef STM32F10X_XL
#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */
#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */
#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */
#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
((FLAG) == FLASH_FLAG_OPTERR)|| \
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
#else
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
((FLAG) == FLASH_FLAG_OPTERR))
#endif
/**
* @}
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions
* @{
*/
/*------------ Functions used for all STM32F10x devices -----*/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
/*------------ New function used for all STM32F10x devices -----*/
void FLASH_UnlockBank1(void);
void FLASH_LockBank1(void);
FLASH_Status FLASH_EraseAllBank1Pages(void);
FLASH_Status FLASH_GetBank1Status(void);
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
#ifdef STM32F10X_XL
/*---- New Functions used only with STM32F10x_XL density devices -----*/
void FLASH_UnlockBank2(void);
void FLASH_LockBank2(void);
FLASH_Status FLASH_EraseAllBank2Pages(void);
FLASH_Status FLASH_GetBank2Status(void);
FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
#endif
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_FLASH_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_fsmc.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FSMC_H
#define __STM32F10x_FSMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup FSMC
* @{
*/
/** @defgroup FSMC_Exported_Types
* @{
*/
/**
* @brief Timing parameters For NOR/SRAM Banks
*/
typedef struct
{
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between 0 and 0xF.
@note: It is not used with synchronous NOR Flash memories. */
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between 0 and 0xF.
@note: It is not used with synchronous NOR Flash memories.*/
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between 0 and 0xFF.
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between 0 and 0xF.
@note: It is only used for multiplexed NOR Flash memories. */
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
This parameter can be a value between 1 and 0xF.
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The value of this parameter depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between 0 and 0xF in NOR Flash memories
with synchronous burst mode enable */
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
}FSMC_NORSRAMTimingInitTypeDef;
/**
* @brief FSMC NOR/SRAM Init structure definition
*/
typedef struct
{
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the databus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory bank.
This parameter can be a value of @ref FSMC_Memory_Type */
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FSMC_Data_Width */
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FSMC_Write_Burst */
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
}FSMC_NORSRAMInitTypeDef;
/**
* @brief Timing parameters For FSMC NAND and PCCARD Banks
*/
typedef struct
{
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between 0 and 0xFF.*/
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command deassertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
databus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */
}FSMC_NAND_PCCARDTimingInitTypeDef;
/**
* @brief FSMC NAND Init structure definition
*/
typedef struct
{
uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
This parameter can be a value of @ref FSMC_NAND_Bank */
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FSMC_Data_Width */
uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FSMC_ECC */
uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FSMC_ECC_Page_Size */
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between 0 and 0xFF. */
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between 0x0 and 0xFF */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
}FSMC_NANDInitTypeDef;
/**
* @brief FSMC PCCARD Init structure definition
*/
typedef struct
{
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between 0 and 0xFF. */
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between 0x0 and 0xFF */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
}FSMC_PCCARDInitTypeDef;
/**
* @}
*/
/** @defgroup FSMC_Exported_Constants
* @{
*/
/** @defgroup FSMC_NORSRAM_Bank
* @{
*/
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
/**
* @}
*/
/** @defgroup FSMC_NAND_Bank
* @{
*/
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
/**
* @}
*/
/** @defgroup FSMC_PCCARD_Bank
* @{
*/
#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
/**
* @}
*/
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
((BANK) == FSMC_Bank1_NORSRAM2) || \
((BANK) == FSMC_Bank1_NORSRAM3) || \
((BANK) == FSMC_Bank1_NORSRAM4))
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND))
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
((BANK) == FSMC_Bank3_NAND) || \
((BANK) == FSMC_Bank4_PCCARD))
/** @defgroup NOR_SRAM_Controller
* @{
*/
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
* @{
*/
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
((MUX) == FSMC_DataAddressMux_Enable))
/**
* @}
*/
/** @defgroup FSMC_Memory_Type
* @{
*/
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
((MEMORY) == FSMC_MemoryType_NOR))
/**
* @}
*/
/** @defgroup FSMC_Data_Width
* @{
*/
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/**
* @}
*/
/** @defgroup FSMC_Burst_Access_Mode
* @{
*/
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
((STATE) == FSMC_BurstAccessMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_AsynchronousWait
* @{
*/
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
((STATE) == FSMC_AsynchronousWait_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal_Polarity
* @{
*/
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
((POLARITY) == FSMC_WaitSignalPolarity_High))
/**
* @}
*/
/** @defgroup FSMC_Wrap_Mode
* @{
*/
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
((MODE) == FSMC_WrapMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Timing
* @{
*/
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
/**
* @}
*/
/** @defgroup FSMC_Write_Operation
* @{
*/
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
((OPERATION) == FSMC_WriteOperation_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal
* @{
*/
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
((SIGNAL) == FSMC_WaitSignal_Enable))
/**
* @}
*/
/** @defgroup FSMC_Extended_Mode
* @{
*/
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
((MODE) == FSMC_ExtendedMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_Write_Burst
* @{
*/
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
((BURST) == FSMC_WriteBurst_Enable))
/**
* @}
*/
/** @defgroup FSMC_Address_Setup_Time
* @{
*/
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Address_Hold_Time
* @{
*/
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Data_Setup_Time
* @{
*/
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
/**
* @}
*/
/** @defgroup FSMC_Bus_Turn_around_Duration
* @{
*/
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_CLK_Division
* @{
*/
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Data_Latency
* @{
*/
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Access_Mode
* @{
*/
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
((MODE) == FSMC_AccessMode_B) || \
((MODE) == FSMC_AccessMode_C) || \
((MODE) == FSMC_AccessMode_D))
/**
* @}
*/
/**
* @}
*/
/** @defgroup NAND_PCCARD_Controller
* @{
*/
/** @defgroup FSMC_Wait_feature
* @{
*/
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
((FEATURE) == FSMC_Waitfeature_Enable))
/**
* @}
*/
/** @defgroup FSMC_ECC
* @{
*/
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
((STATE) == FSMC_ECC_Enable))
/**
* @}
*/
/** @defgroup FSMC_ECC_Page_Size
* @{
*/
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
((SIZE) == FSMC_ECCPageSize_8192Bytes))
/**
* @}
*/
/** @defgroup FSMC_TCLR_Setup_Time
* @{
*/
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_TAR_Setup_Time
* @{
*/
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Setup_Time
* @{
*/
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Wait_Setup_Time
* @{
*/
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Hold_Setup_Time
* @{
*/
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_HiZ_Setup_Time
* @{
*/
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
/**
* @}
*/
/** @defgroup FSMC_Interrupt_sources
* @{
*/
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
#define FSMC_IT_Level ((uint32_t)0x00000010)
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
((IT) == FSMC_IT_Level) || \
((IT) == FSMC_IT_FallingEdge))
/**
* @}
*/
/** @defgroup FSMC_Flags
* @{
*/
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
#define FSMC_FLAG_Level ((uint32_t)0x00000002)
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
((FLAG) == FSMC_FLAG_Level) || \
((FLAG) == FSMC_FLAG_FallingEdge) || \
((FLAG) == FSMC_FLAG_FEMPT))
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/** @defgroup FSMC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup FSMC_Exported_Functions
* @{
*/
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
void FSMC_PCCARDDeInit(void);
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
void FSMC_PCCARDCmd(FunctionalState NewState);
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_FSMC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_gpio.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_GPIO_H
#define __STM32F10x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** @defgroup GPIO_Exported_Types
* @{
*/
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC) || \
((PERIPH) == GPIOD) || \
((PERIPH) == GPIOE) || \
((PERIPH) == GPIOF) || \
((PERIPH) == GPIOG))
/**
* @brief Output Maximum frequency selection
*/
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
}GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
((SPEED) == GPIO_Speed_50MHz))
/**
* @brief Configuration Mode enumeration
*/
typedef enum
{ GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_IPD = 0x28,
GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14,
GPIO_Mode_Out_PP = 0x10,
GPIO_Mode_AF_OD = 0x1C,
GPIO_Mode_AF_PP = 0x18
}GPIOMode_TypeDef;
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
}GPIO_InitTypeDef;
/**
* @brief Bit_SET and Bit_RESET enumeration
*/
typedef enum
{ Bit_RESET = 0,
Bit_SET
}BitAction;
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
/**
* @}
*/
/** @defgroup GPIO_Exported_Constants
* @{
*/
/** @defgroup GPIO_pins_define
* @{
*/
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
((PIN) == GPIO_Pin_3) || \
((PIN) == GPIO_Pin_4) || \
((PIN) == GPIO_Pin_5) || \
((PIN) == GPIO_Pin_6) || \
((PIN) == GPIO_Pin_7) || \
((PIN) == GPIO_Pin_8) || \
((PIN) == GPIO_Pin_9) || \
((PIN) == GPIO_Pin_10) || \
((PIN) == GPIO_Pin_11) || \
((PIN) == GPIO_Pin_12) || \
((PIN) == GPIO_Pin_13) || \
((PIN) == GPIO_Pin_14) || \
((PIN) == GPIO_Pin_15))
/**
* @}
*/
/** @defgroup GPIO_Remap_define
* @{
*/
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
to TIM2 Internal Trigger 1 for calibration
(only for Connectivity line devices) */
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */
#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */
#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */
#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
only for High density Value line devices) */
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
/**
* @}
*/
/** @defgroup GPIO_Port_Sources
* @{
*/
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
((PORTSOURCE) == GPIO_PortSourceGPIOE))
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
((PORTSOURCE) == GPIO_PortSourceGPIOG))
/**
* @}
*/
/** @defgroup GPIO_Pin_sources
* @{
*/
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
((PINSOURCE) == GPIO_PinSource1) || \
((PINSOURCE) == GPIO_PinSource2) || \
((PINSOURCE) == GPIO_PinSource3) || \
((PINSOURCE) == GPIO_PinSource4) || \
((PINSOURCE) == GPIO_PinSource5) || \
((PINSOURCE) == GPIO_PinSource6) || \
((PINSOURCE) == GPIO_PinSource7) || \
((PINSOURCE) == GPIO_PinSource8) || \
((PINSOURCE) == GPIO_PinSource9) || \
((PINSOURCE) == GPIO_PinSource10) || \
((PINSOURCE) == GPIO_PinSource11) || \
((PINSOURCE) == GPIO_PinSource12) || \
((PINSOURCE) == GPIO_PinSource13) || \
((PINSOURCE) == GPIO_PinSource14) || \
((PINSOURCE) == GPIO_PinSource15))
/**
* @}
*/
/** @defgroup Ethernet_Media_Interface
* @{
*/
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
/**
* @}
*/
/**
* @}
*/
/** @defgroup GPIO_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions
* @{
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_GPIO_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_i2c.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_I2C_H
#define __STM32F10x_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/** @defgroup I2C_Exported_Types
* @{
*/
/**
* @brief I2C Init structure definition
*/
typedef struct
{
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
}I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup I2C_Exported_Constants
* @{
*/
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
((PERIPH) == I2C2))
/** @defgroup I2C_mode
* @{
*/
#define I2C_Mode_I2C ((uint16_t)0x0000)
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
((MODE) == I2C_Mode_SMBusDevice) || \
((MODE) == I2C_Mode_SMBusHost))
/**
* @}
*/
/** @defgroup I2C_duty_cycle_in_fast_mode
* @{
*/
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
((CYCLE) == I2C_DutyCycle_2))
/**
* @}
*/
/** @defgroup I2C_acknowledgement
* @{
*/
#define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000)
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
((STATE) == I2C_Ack_Disable))
/**
* @}
*/
/** @defgroup I2C_transfer_direction
* @{
*/
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
((DIRECTION) == I2C_Direction_Receiver))
/**
* @}
*/
/** @defgroup I2C_acknowledged_address
* @{
*/
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
/**
* @}
*/
/** @defgroup I2C_registers
* @{
*/
#define I2C_Register_CR1 ((uint8_t)0x00)
#define I2C_Register_CR2 ((uint8_t)0x04)
#define I2C_Register_OAR1 ((uint8_t)0x08)
#define I2C_Register_OAR2 ((uint8_t)0x0C)
#define I2C_Register_DR ((uint8_t)0x10)
#define I2C_Register_SR1 ((uint8_t)0x14)
#define I2C_Register_SR2 ((uint8_t)0x18)
#define I2C_Register_CCR ((uint8_t)0x1C)
#define I2C_Register_TRISE ((uint8_t)0x20)
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
((REGISTER) == I2C_Register_CR2) || \
((REGISTER) == I2C_Register_OAR1) || \
((REGISTER) == I2C_Register_OAR2) || \
((REGISTER) == I2C_Register_DR) || \
((REGISTER) == I2C_Register_SR1) || \
((REGISTER) == I2C_Register_SR2) || \
((REGISTER) == I2C_Register_CCR) || \
((REGISTER) == I2C_Register_TRISE))
/**
* @}
*/
/** @defgroup I2C_SMBus_alert_pin_level
* @{
*/
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
((ALERT) == I2C_SMBusAlert_High))
/**
* @}
*/
/** @defgroup I2C_PEC_position
* @{
*/
#define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
((POSITION) == I2C_PECPosition_Current))
/**
* @}
*/
/** @defgroup I2C_NCAK_position
* @{
*/
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
((POSITION) == I2C_NACKPosition_Current))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200)
#define I2C_IT_ERR ((uint16_t)0x0100)
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002)
#define I2C_IT_SB ((uint32_t)0x02000001)
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
/**
* @}
*/
/** @defgroup I2C_flags_definition
* @{
*/
/**
* @brief SR2 register flags
*/
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
/**
* @brief SR1 register flags
*/
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define I2C_FLAG_SB ((uint32_t)0x10000001)
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
((FLAG) == I2C_FLAG_SB))
/**
* @}
*/
/** @defgroup I2C_Events
* @{
*/
/*========================================
I2C Master Events (Events grouped in order of communication)
==========================================*/
/**
* @brief Communication start
*
* After sending the START condition (I2C_GenerateSTART() function) the master
* has to wait for this event. It means that the Start condition has been correctly
* released on the I2C bus (the bus is free, no other devices is communicating).
*
*/
/* --EV5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
/**
* @brief Address Acknowledge
*
* After checking on EV5 (start condition correctly released on the bus), the
* master sends the address of the slave(s) with which it will communicate
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
* his address. If an acknowledge is sent on the bus, one of the following events will
* be set:
*
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
* event is set.
*
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
* is set
*
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
* function). Then master should wait on EV9. It means that the 10-bit addressing
* header has been correctly sent on the bus. Then master should send the second part of
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
* should wait for event EV6.
*
*/
/* --EV6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
/* --EV9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
/**
* @brief Communication events
*
* If a communication is established (START condition generated and slave address
* acknowledged) then the master has to check on one of the following events for
* communication procedures:
*
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
* the data received from the slave (I2C_ReceiveData() function).
*
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
* function) then to wait on event EV8 or EV8_2.
* These two events are similar:
* - EV8 means that the data has been written in the data register and is
* being shifted out.
* - EV8_2 means that the data has been physically shifted out and output
* on the bus.
* In most cases, using EV8 is sufficient for the application.
* Using EV8_2 leads to a slower communication but ensure more reliable test.
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
* (before Stop condition generation).
*
* @note In case the user software does not guarantee that this event EV7 is
* managed before the current byte end of transfer, then user may check on EV7
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Master RECEIVER mode -----------------------------*/
/* --EV7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/* Master TRANSMITTER mode --------------------------*/
/* --EV8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/* --EV8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/*========================================
I2C Slave Events (Events grouped in order of communication)
==========================================*/
/**
* @brief Communication start events
*
* Wait on one of these events at the start of the communication. It means that
* the I2C peripheral detected a Start condition on the bus (generated by master
* device) followed by the peripheral address. The peripheral generates an ACK
* condition on the bus (if the acknowledge feature is enabled through function
* I2C_AcknowledgeConfig()) and the events listed above are set :
*
* 1) In normal case (only one address managed by the slave), when the address
* sent by the master matches the own address of the peripheral (configured by
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
* (where XXX could be TRANSMITTER or RECEIVER).
*
* 2) In case the address sent by the master matches the second address of the
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
* (where XXX could be TRANSMITTER or RECEIVER) are set.
*
* 3) In case the address sent by the master is General Call (address 0x00) and
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
*
*/
/* --EV1 (all the events below are variants of EV1) */
/* 1) Case of One Single Address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
/* 2) Case of Dual address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
/* 3) Case of General Call enabled for the slave */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/**
* @brief Communication events
*
* Wait on one of these events when EV1 has already been checked and:
*
* - Slave RECEIVER mode:
* - EV2: When the application is expecting a data byte to be received.
* - EV4: When the application is expecting the end of the communication: master
* sends a stop condition and data transmission is stopped.
*
* - Slave Transmitter mode:
* - EV3: When a byte has been transmitted by the slave and the application is expecting
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
* used when the user software doesn't guarantee the EV3 is managed before the
* current byte end of transfer.
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
* shall end (before sending the STOP condition). In this case slave has to stop sending
* data bytes and expect a Stop condition on the bus.
*
* @note In case the user software does not guarantee that the event EV2 is
* managed before the current byte end of transfer, then user may check on EV2
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Slave RECEIVER mode --------------------------*/
/* --EV2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/* --EV4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/* Slave TRANSMITTER mode -----------------------*/
/* --EV3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
/* --EV3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
/*=========================== End of Events Description ==========================================*/
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
/**
* @}
*/
/** @defgroup I2C_own_address1
* @{
*/
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
/**
* @}
*/
/** @defgroup I2C_clock_speed
* @{
*/
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
/**
* @}
*/
/**
* @}
*/
/** @defgroup I2C_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup I2C_Exported_Functions
* @{
*/
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
/**
* @brief
****************************************************************************************
*
* I2C State Monitoring Functions
*
****************************************************************************************
* This I2C driver provides three different ways for I2C state monitoring
* depending on the application requirements and constraints:
*
*
* 1) Basic state monitoring:
* Using I2C_CheckEvent() function:
* It compares the status registers (SR1 and SR2) content to a given event
* (can be the combination of one or more flags).
* It returns SUCCESS if the current status includes the given flags
* and returns ERROR if one or more flags are missing in the current status.
* - When to use:
* - This function is suitable for most applications as well as for startup
* activity since the events are fully described in the product reference manual
* (RM0008).
* - It is also suitable for users who need to define their own events.
* - Limitations:
* - If an error occurs (ie. error flags are set besides to the monitored flags),
* the I2C_CheckEvent() function may return SUCCESS despite the communication
* hold or corrupted real state.
* In this case, it is advised to use error interrupts to monitor the error
* events and handle them in the interrupt IRQ handler.
*
* @note
* For error management, it is advised to use the following functions:
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
* - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
* Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
* in order to determine which error occurred.
* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
* and/or I2C_GenerateStop() in order to clear the error flag and source,
* and return to correct communication status.
*
*
* 2) Advanced state monitoring:
* Using the function I2C_GetLastEvent() which returns the image of both status
* registers in a single word (uint32_t) (Status Register 2 value is shifted left
* by 16 bits and concatenated to Status Register 1).
* - When to use:
* - This function is suitable for the same applications above but it allows to
* overcome the limitations of I2C_GetFlagStatus() function (see below).
* The returned value could be compared to events already defined in the
* library (stm32f10x_i2c.h) or to custom values defined by user.
* - This function is suitable when multiple flags are monitored at the same time.
* - At the opposite of I2C_CheckEvent() function, this function allows user to
* choose when an event is accepted (when all events flags are set and no
* other flags are set or just when the needed flags are set like
* I2C_CheckEvent() function).
* - Limitations:
* - User may need to define his own events.
* - Same remark concerning the error management is applicable for this
* function if user decides to check only regular communication flags (and
* ignores error flags).
*
*
* 3) Flag-based state monitoring:
* Using the function I2C_GetFlagStatus() which simply returns the status of
* one single flag (ie. I2C_FLAG_RXNE ...).
* - When to use:
* - This function could be used for specific applications or in debug phase.
* - It is suitable when only one flag checking is needed (most I2C events
* are monitored through multiple flags).
* - Limitations:
* - When calling this function, the Status register is accessed. Some flags are
* cleared when the status register is accessed. So checking the status
* of one Flag, may clear other ones.
* - Function may need to be called twice or more in order to monitor one
* single event.
*
*/
/**
*
* 1) Basic state monitoring
*******************************************************************************
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
/**
*
* 2) Advanced state monitoring
*******************************************************************************
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/**
*
* 3) Flag-based state monitoring
*******************************************************************************
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
/**
*
*******************************************************************************
*/
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_I2C_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_iwdg.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_IWDG_H
#define __STM32F10x_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup IWDG
* @{
*/
/** @defgroup IWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Constants
* @{
*/
/** @defgroup IWDG_WriteAccess
* @{
*/
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
((ACCESS) == IWDG_WriteAccess_Disable))
/**
* @}
*/
/** @defgroup IWDG_prescaler
* @{
*/
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06)
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
((PRESCALER) == IWDG_Prescaler_8) || \
((PRESCALER) == IWDG_Prescaler_16) || \
((PRESCALER) == IWDG_Prescaler_32) || \
((PRESCALER) == IWDG_Prescaler_64) || \
((PRESCALER) == IWDG_Prescaler_128)|| \
((PRESCALER) == IWDG_Prescaler_256))
/**
* @}
*/
/** @defgroup IWDG_Flag
* @{
*/
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
/**
* @}
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions
* @{
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_IWDG_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_pwr.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_PWR_H
#define __STM32F10x_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/** @defgroup PWR_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Constants
* @{
*/
/** @defgroup PVD_detection_level
* @{
*/
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
/**
* @}
*/
/** @defgroup Regulator_state_is_STOP_mode
* @{
*/
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
((REGULATOR) == PWR_Regulator_LowPower))
/**
* @}
*/
/** @defgroup STOP_mode_entry
* @{
*/
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/**
* @}
*/
/** @defgroup PWR_Flag
* @{
*/
#define PWR_FLAG_WU ((uint32_t)0x00000001)
#define PWR_FLAG_SB ((uint32_t)0x00000002)
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/**
* @}
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Functions
* @{
*/
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_PWR_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_rcc.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the RCC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RCC_H
#define __STM32F10x_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup RCC
* @{
*/
/** @defgroup RCC_Exported_Types
* @{
*/
typedef struct
{
uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
}RCC_ClocksTypeDef;
/**
* @}
*/
/** @defgroup RCC_Exported_Constants
* @{
*/
/** @defgroup HSE_configuration
* @{
*/
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000)
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))
/**
* @}
*/
/** @defgroup PLL_entry_clock_source
* @{
*/
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_HSE_Div1) || \
((SOURCE) == RCC_PLLSource_HSE_Div2))
#else
#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
((SOURCE) == RCC_PLLSource_PREDIV1))
#endif /* STM32F10X_CL */
/**
* @}
*/
/** @defgroup PLL_multiplication_factor
* @{
*/
#ifndef STM32F10X_CL
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
((MUL) == RCC_PLLMul_16))
#else
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_6_5))
#endif /* STM32F10X_CL */
/**
* @}
*/
/** @defgroup PREDIV1_division_factor
* @{
*/
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
#endif
/**
* @}
*/
/** @defgroup PREDIV1_clock_source
* @{
*/
#ifdef STM32F10X_CL
/* PREDIV1 clock source (for STM32 connectivity line devices) */
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
((SOURCE) == RCC_PREDIV1_Source_PLL2))
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/* PREDIV1 clock source (for STM32 Value line devices) */
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
#endif
/**
* @}
*/
#ifdef STM32F10X_CL
/** @defgroup PREDIV2_division_factor
* @{
*/
#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
#define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
/**
* @}
*/
/** @defgroup PLL2_multiplication_factor
* @{
*/
#define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
#define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
#define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
#define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
#define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
((MUL) == RCC_PLL2Mul_20))
/**
* @}
*/
/** @defgroup PLL3_multiplication_factor
* @{
*/
#define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
#define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
#define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
#define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
#define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
((MUL) == RCC_PLL3Mul_20))
/**
* @}
*/
#endif /* STM32F10X_CL */
/** @defgroup System_clock_source
* @{
*/
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
/**
* @}
*/
/** @defgroup AHB_clock_source
* @{
*/
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
/**
* @}
*/
/** @defgroup APB1_APB2_clock_source
* @{
*/
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))
/**
* @}
*/
/** @defgroup RCC_Interrupt_source
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80)
#ifndef STM32F10X_CL
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
#else
#define RCC_IT_PLL2RDY ((uint8_t)0x20)
#define RCC_IT_PLL3RDY ((uint8_t)0x40)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
#endif /* STM32F10X_CL */
/**
* @}
*/
#ifndef STM32F10X_CL
/** @defgroup USB_Device_clock_source
* @{
*/
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
/**
* @}
*/
#else
/** @defgroup USB_OTG_FS_clock_source
* @{
*/
#define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
#define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
#define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
/**
* @}
*/
#endif /* STM32F10X_CL */
#ifdef STM32F10X_CL
/** @defgroup I2S2_clock_source
* @{
*/
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
#define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
/**
* @}
*/
/** @defgroup I2S3_clock_source
* @{
*/
#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
#define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
/**
* @}
*/
#endif /* STM32F10X_CL */
/** @defgroup ADC_clock_source
* @{
*/
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
/**
* @}
*/
/** @defgroup LSE_configuration
* @{
*/
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_Bypass ((uint8_t)0x04)
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))
/**
* @}
*/
/** @defgroup RTC_clock_source
* @{
*/
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
/**
* @}
*/
/** @defgroup AHB_peripheral
* @{
*/
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
#ifndef STM32F10X_CL
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
#else
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
#endif /* STM32F10X_CL */
/**
* @}
*/
/** @defgroup APB2_peripheral
* @{
*/
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup APB1_peripheral
* @{
*/
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup Clock_source_to_output_on_MCO_pin
* @{
*/
#define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_HSI ((uint8_t)0x05)
#define RCC_MCO_HSE ((uint8_t)0x06)
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
#ifndef STM32F10X_CL
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
((MCO) == RCC_MCO_PLLCLK_Div2))
#else
#define RCC_MCO_PLL2CLK ((uint8_t)0x08)
#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
#define RCC_MCO_XT1 ((uint8_t)0x0A)
#define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
((MCO) == RCC_MCO_PLL3CLK))
#endif /* STM32F10X_CL */
/**
* @}
*/
/** @defgroup RCC_Flag
* @{
*/
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#ifndef STM32F10X_CL
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
((FLAG) == RCC_FLAG_LPWRRST))
#else
#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
((FLAG) == RCC_FLAG_LPWRRST))
#endif /* STM32F10X_CL */
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
* @}
*/
/**
* @}
*/
/** @defgroup RCC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup RCC_Exported_Functions
* @{
*/
void RCC_DeInit(void);
void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
#endif
#ifdef STM32F10X_CL
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
void RCC_PLL2Cmd(FunctionalState NewState);
void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
void RCC_PLL3Cmd(FunctionalState NewState);
#endif /* STM32F10X_CL */
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
#ifndef STM32F10X_CL
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
#else
void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
#endif /* STM32F10X_CL */
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
#ifdef STM32F10X_CL
void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
#endif /* STM32F10X_CL */
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
#ifdef STM32F10X_CL
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
#endif /* STM32F10X_CL */
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCO);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_RCC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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FWLIB/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h Normal file
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@@ -0,0 +1,135 @@
/**
******************************************************************************
* @file stm32f10x_rtc.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_RTC_H
#define __STM32F10x_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup RTC
* @{
*/
/** @defgroup RTC_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Constants
* @{
*/
/** @defgroup RTC_interrupts_define
* @{
*/
#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
((IT) == RTC_IT_SEC))
/**
* @}
*/
/** @defgroup RTC_interrupts_flags
* @{
*/
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
((FLAG) == RTC_FLAG_SEC))
#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
/**
* @}
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Functions
* @{
*/
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
uint32_t RTC_GetCounter(void);
void RTC_SetCounter(uint32_t CounterValue);
void RTC_SetPrescaler(uint32_t PrescalerValue);
void RTC_SetAlarm(uint32_t AlarmValue);
uint32_t RTC_GetDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchro(void);
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
void RTC_ClearFlag(uint16_t RTC_FLAG);
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
void RTC_ClearITPendingBit(uint16_t RTC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_RTC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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FWLIB/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h Normal file
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/**
******************************************************************************
* @file stm32f10x_sdio.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SDIO_H
#define __STM32F10x_SDIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup SDIO
* @{
*/
/** @defgroup SDIO_Exported_Types
* @{
*/
typedef struct
{
uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref SDIO_Clock_Edge */
uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
enabled or disabled.
This parameter can be a value of @ref SDIO_Clock_Bypass */
uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
disabled when the bus is idle.
This parameter can be a value of @ref SDIO_Clock_Power_Save */
uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
This parameter can be a value of @ref SDIO_Bus_Wide */
uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
This parameter can be a value between 0x00 and 0xFF. */
} SDIO_InitTypeDef;
typedef struct
{
uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
to a card as part of a command message. If a command
contains an argument, it must be loaded into this register
before writing the command to the command register */
uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
This parameter can be a value of @ref SDIO_Response_Type */
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_CPSM_State */
} SDIO_CmdInitTypeDef;
typedef struct
{
uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
This parameter can be a value of @ref SDIO_Data_Block_Size */
uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
is a read or write.
This parameter can be a value of @ref SDIO_Transfer_Direction */
uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
This parameter can be a value of @ref SDIO_Transfer_Type */
uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_DPSM_State */
} SDIO_DataInitTypeDef;
/**
* @}
*/
/** @defgroup SDIO_Exported_Constants
* @{
*/
/** @defgroup SDIO_Clock_Edge
* @{
*/
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
((EDGE) == SDIO_ClockEdge_Falling))
/**
* @}
*/
/** @defgroup SDIO_Clock_Bypass
* @{
*/
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
((BYPASS) == SDIO_ClockBypass_Enable))
/**
* @}
*/
/** @defgroup SDIO_Clock_Power_Save
* @{
*/
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
((SAVE) == SDIO_ClockPowerSave_Enable))
/**
* @}
*/
/** @defgroup SDIO_Bus_Wide
* @{
*/
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
((WIDE) == SDIO_BusWide_8b))
/**
* @}
*/
/** @defgroup SDIO_Hardware_Flow_Control
* @{
*/
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
((CONTROL) == SDIO_HardwareFlowControl_Enable))
/**
* @}
*/
/** @defgroup SDIO_Power_State
* @{
*/
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
/**
* @}
*/
/** @defgroup SDIO_Interrupt_sources
* @{
*/
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Command_Index
* @{
*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
/**
* @}
*/
/** @defgroup SDIO_Response_Type
* @{
*/
#define SDIO_Response_No ((uint32_t)0x00000000)
#define SDIO_Response_Short ((uint32_t)0x00000040)
#define SDIO_Response_Long ((uint32_t)0x000000C0)
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
((RESPONSE) == SDIO_Response_Short) || \
((RESPONSE) == SDIO_Response_Long))
/**
* @}
*/
/** @defgroup SDIO_Wait_Interrupt_State
* @{
*/
#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
((WAIT) == SDIO_Wait_Pend))
/**
* @}
*/
/** @defgroup SDIO_CPSM_State
* @{
*/
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
/**
* @}
*/
/** @defgroup SDIO_Response_Registers
* @{
*/
#define SDIO_RESP1 ((uint32_t)0x00000000)
#define SDIO_RESP2 ((uint32_t)0x00000004)
#define SDIO_RESP3 ((uint32_t)0x00000008)
#define SDIO_RESP4 ((uint32_t)0x0000000C)
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
/**
* @}
*/
/** @defgroup SDIO_Data_Length
* @{
*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
/**
* @}
*/
/** @defgroup SDIO_Data_Block_Size
* @{
*/
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
((SIZE) == SDIO_DataBlockSize_2b) || \
((SIZE) == SDIO_DataBlockSize_4b) || \
((SIZE) == SDIO_DataBlockSize_8b) || \
((SIZE) == SDIO_DataBlockSize_16b) || \
((SIZE) == SDIO_DataBlockSize_32b) || \
((SIZE) == SDIO_DataBlockSize_64b) || \
((SIZE) == SDIO_DataBlockSize_128b) || \
((SIZE) == SDIO_DataBlockSize_256b) || \
((SIZE) == SDIO_DataBlockSize_512b) || \
((SIZE) == SDIO_DataBlockSize_1024b) || \
((SIZE) == SDIO_DataBlockSize_2048b) || \
((SIZE) == SDIO_DataBlockSize_4096b) || \
((SIZE) == SDIO_DataBlockSize_8192b) || \
((SIZE) == SDIO_DataBlockSize_16384b))
/**
* @}
*/
/** @defgroup SDIO_Transfer_Direction
* @{
*/
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
((DIR) == SDIO_TransferDir_ToSDIO))
/**
* @}
*/
/** @defgroup SDIO_Transfer_Type
* @{
*/
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
((MODE) == SDIO_TransferMode_Block))
/**
* @}
*/
/** @defgroup SDIO_DPSM_State
* @{
*/
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
/**
* @}
*/
/** @defgroup SDIO_Flags
* @{
*/
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
((FLAG) == SDIO_FLAG_TXUNDERR) || \
((FLAG) == SDIO_FLAG_RXOVERR) || \
((FLAG) == SDIO_FLAG_CMDREND) || \
((FLAG) == SDIO_FLAG_CMDSENT) || \
((FLAG) == SDIO_FLAG_DATAEND) || \
((FLAG) == SDIO_FLAG_STBITERR) || \
((FLAG) == SDIO_FLAG_DBCKEND) || \
((FLAG) == SDIO_FLAG_CMDACT) || \
((FLAG) == SDIO_FLAG_TXACT) || \
((FLAG) == SDIO_FLAG_RXACT) || \
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
((FLAG) == SDIO_FLAG_TXFIFOF) || \
((FLAG) == SDIO_FLAG_RXFIFOF) || \
((FLAG) == SDIO_FLAG_TXFIFOE) || \
((FLAG) == SDIO_FLAG_RXFIFOE) || \
((FLAG) == SDIO_FLAG_TXDAVL) || \
((FLAG) == SDIO_FLAG_RXDAVL) || \
((FLAG) == SDIO_FLAG_SDIOIT) || \
((FLAG) == SDIO_FLAG_CEATAEND))
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
((IT) == SDIO_IT_DCRCFAIL) || \
((IT) == SDIO_IT_CTIMEOUT) || \
((IT) == SDIO_IT_DTIMEOUT) || \
((IT) == SDIO_IT_TXUNDERR) || \
((IT) == SDIO_IT_RXOVERR) || \
((IT) == SDIO_IT_CMDREND) || \
((IT) == SDIO_IT_CMDSENT) || \
((IT) == SDIO_IT_DATAEND) || \
((IT) == SDIO_IT_STBITERR) || \
((IT) == SDIO_IT_DBCKEND) || \
((IT) == SDIO_IT_CMDACT) || \
((IT) == SDIO_IT_TXACT) || \
((IT) == SDIO_IT_RXACT) || \
((IT) == SDIO_IT_TXFIFOHE) || \
((IT) == SDIO_IT_RXFIFOHF) || \
((IT) == SDIO_IT_TXFIFOF) || \
((IT) == SDIO_IT_RXFIFOF) || \
((IT) == SDIO_IT_TXFIFOE) || \
((IT) == SDIO_IT_RXFIFOE) || \
((IT) == SDIO_IT_TXDAVL) || \
((IT) == SDIO_IT_RXDAVL) || \
((IT) == SDIO_IT_SDIOIT) || \
((IT) == SDIO_IT_CEATAEND))
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Read_Wait_Mode
* @{
*/
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
((MODE) == SDIO_ReadWaitMode_DATA2))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SDIO_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SDIO_Exported_Functions
* @{
*/
void SDIO_DeInit(void);
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_ClockCmd(FunctionalState NewState);
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
uint32_t SDIO_GetPowerState(void);
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
void SDIO_DMACmd(FunctionalState NewState);
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
uint8_t SDIO_GetCommandResponse(void);
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
uint32_t SDIO_GetDataCounter(void);
uint32_t SDIO_ReadData(void);
void SDIO_WriteData(uint32_t Data);
uint32_t SDIO_GetFIFOCount(void);
void SDIO_StartSDIOReadWait(FunctionalState NewState);
void SDIO_StopSDIOReadWait(FunctionalState NewState);
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
void SDIO_SetSDIOOperation(FunctionalState NewState);
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
void SDIO_CommandCompletionCmd(FunctionalState NewState);
void SDIO_CEATAITCmd(FunctionalState NewState);
void SDIO_SendCEATACmd(FunctionalState NewState);
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_SDIO_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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FWLIB/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h Normal file
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@@ -0,0 +1,487 @@
/**
******************************************************************************
* @file stm32f10x_spi.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_SPI_H
#define __STM32F10x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @defgroup SPI_Exported_Types
* @{
*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
}SPI_InitTypeDef;
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
}I2S_InitTypeDef;
/**
* @}
*/
/** @defgroup SPI_Exported_Constants
* @{
*/
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \
((PERIPH) == SPI3))
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3))
/** @defgroup SPI_data_direction
* @{
*/
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
((MODE) == SPI_Direction_2Lines_RxOnly) || \
((MODE) == SPI_Direction_1Line_Rx) || \
((MODE) == SPI_Direction_1Line_Tx))
/**
* @}
*/
/** @defgroup SPI_mode
* @{
*/
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
/**
* @}
*/
/** @defgroup SPI_data_size
* @{
*/
#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
((DATASIZE) == SPI_DataSize_8b))
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity
* @{
*/
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_Clock_Phase
* @{
*/
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
/**
* @}
*/
/** @defgroup SPI_Slave_Select_management
* @{
*/
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
((NSS) == SPI_NSS_Hard))
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler
* @{
*/
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
((PRESCALER) == SPI_BaudRatePrescaler_256))
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission
* @{
*/
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
((BIT) == SPI_FirstBit_LSB))
/**
* @}
*/
/** @defgroup I2S_Mode
* @{
*/
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
((MODE) == I2S_Mode_SlaveRx) || \
((MODE) == I2S_Mode_MasterTx) || \
((MODE) == I2S_Mode_MasterRx) )
/**
* @}
*/
/** @defgroup I2S_Standard
* @{
*/
#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
((STANDARD) == I2S_Standard_MSB) || \
((STANDARD) == I2S_Standard_LSB) || \
((STANDARD) == I2S_Standard_PCMShort) || \
((STANDARD) == I2S_Standard_PCMLong))
/**
* @}
*/
/** @defgroup I2S_Data_Format
* @{
*/
#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
((FORMAT) == I2S_DataFormat_16bextended) || \
((FORMAT) == I2S_DataFormat_24b) || \
((FORMAT) == I2S_DataFormat_32b))
/**
* @}
*/
/** @defgroup I2S_MCLK_Output
* @{
*/
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
((OUTPUT) == I2S_MCLKOutput_Disable))
/**
* @}
*/
/** @defgroup I2S_Audio_Frequency
* @{
*/
#define I2S_AudioFreq_192k ((uint32_t)192000)
#define I2S_AudioFreq_96k ((uint32_t)96000)
#define I2S_AudioFreq_48k ((uint32_t)48000)
#define I2S_AudioFreq_44k ((uint32_t)44100)
#define I2S_AudioFreq_32k ((uint32_t)32000)
#define I2S_AudioFreq_22k ((uint32_t)22050)
#define I2S_AudioFreq_16k ((uint32_t)16000)
#define I2S_AudioFreq_11k ((uint32_t)11025)
#define I2S_AudioFreq_8k ((uint32_t)8000)
#define I2S_AudioFreq_Default ((uint32_t)2)
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
((FREQ) <= I2S_AudioFreq_192k)) || \
((FREQ) == I2S_AudioFreq_Default))
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity
* @{
*/
#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
((CPOL) == I2S_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_I2S_DMA_transfer_requests
* @{
*/
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
/**
* @}
*/
/** @defgroup SPI_NSS_internal_software_management
* @{
*/
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
((INTERNAL) == SPI_NSSInternalSoft_Reset))
/**
* @}
*/
/** @defgroup SPI_CRC_Transmit_Receive
* @{
*/
#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
/**
* @}
*/
/** @defgroup SPI_direction_transmit_receive
* @{
*/
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx))
/**
* @}
*/
/** @defgroup SPI_I2S_interrupts_definition
* @{
*/
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_I2S_IT_RXNE) || \
((IT) == SPI_I2S_IT_ERR))
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54)
#define I2S_IT_UDR ((uint8_t)0x53)
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
/**
* @}
*/
/** @defgroup SPI_I2S_flags_definition
* @{
*/
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
/**
* @}
*/
/** @defgroup SPI_CRC_polynomial
* @{
*/
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
/**
* @}
*/
/**
* @}
*/
/** @defgroup SPI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Exported_Functions
* @{
*/
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F10x_SPI_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_usart.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_USART_H
#define __STM32F10x_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/** @defgroup USART_Exported_Types
* @{
*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef;
/**
* @brief USART Clock Init Structure definition
*/
typedef struct
{
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/**
* @}
*/
/** @defgroup USART_Exported_Constants
* @{
*/
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
((PERIPH) == UART4) || \
((PERIPH) == UART5))
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3))
#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
((PERIPH) == UART4))
/** @defgroup USART_Word_Length
* @{
*/
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000)
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
((LENGTH) == USART_WordLength_9b))
/**
* @}
*/
/** @defgroup USART_Stop_Bits
* @{
*/
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
#define USART_StopBits_1_5 ((uint16_t)0x3000)
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
((STOPBITS) == USART_StopBits_0_5) || \
((STOPBITS) == USART_StopBits_2) || \
((STOPBITS) == USART_StopBits_1_5))
/**
* @}
*/
/** @defgroup USART_Parity
* @{
*/
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
#define USART_Parity_Odd ((uint16_t)0x0600)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
((PARITY) == USART_Parity_Even) || \
((PARITY) == USART_Parity_Odd))
/**
* @}
*/
/** @defgroup USART_Mode
* @{
*/
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008)
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
/**
* @}
*/
/** @defgroup USART_Hardware_Flow_Control
* @{
*/
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == USART_HardwareFlowControl_None) || \
((CONTROL) == USART_HardwareFlowControl_RTS) || \
((CONTROL) == USART_HardwareFlowControl_CTS) || \
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
/**
* @}
*/
/** @defgroup USART_Clock
* @{
*/
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800)
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
((CLOCK) == USART_Clock_Enable))
/**
* @}
*/
/** @defgroup USART_Clock_Polarity
* @{
*/
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400)
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
/**
* @}
*/
/** @defgroup USART_Clock_Phase
* @{
*/
#define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200)
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
/**
* @}
*/
/** @defgroup USART_Last_Bit
* @{
*/
#define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100)
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
((LASTBIT) == USART_LastBit_Enable))
/**
* @}
*/
/** @defgroup USART_Interrupt_definition
* @{
*/
#define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE ((uint16_t)0x0360)
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
/**
* @}
*/
/** @defgroup USART_DMA_Requests
* @{
*/
#define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040)
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
/**
* @}
*/
/** @defgroup USART_WakeUp_methods
* @{
*/
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
((WAKEUP) == USART_WakeUp_AddressMark))
/**
* @}
*/
/** @defgroup USART_LIN_Break_Detection_Length
* @{
*/
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
((LENGTH) == USART_LINBreakDetectLength_11b))
/**
* @}
*/
/** @defgroup USART_IrDA_Low_Power
* @{
*/
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
((MODE) == USART_IrDAMode_Normal))
/**
* @}
*/
/** @defgroup USART_Flags
* @{
*/
#define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_LBD ((uint16_t)0x0100)
#define USART_FLAG_TXE ((uint16_t)0x0080)
#define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_RXNE ((uint16_t)0x0020)
#define USART_FLAG_IDLE ((uint16_t)0x0010)
#define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001)
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
|| ((USART_FLAG) != USART_FLAG_CTS))
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
/**
* @}
*/
/**
* @}
*/
/** @defgroup USART_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup USART_Exported_Functions
* @{
*/
void USART_DeInit(USART_TypeDef* USARTx);
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
void USART_SendBreak(USART_TypeDef* USARTx);
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_USART_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_wwdg.h
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file contains all the functions prototypes for the WWDG firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_WWDG_H
#define __STM32F10x_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/** @defgroup WWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Constants
* @{
*/
/** @defgroup WWDG_Prescaler
* @{
*/
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
((PRESCALER) == WWDG_Prescaler_2) || \
((PRESCALER) == WWDG_Prescaler_4) || \
((PRESCALER) == WWDG_Prescaler_8))
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
/**
* @}
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Functions
* @{
*/
void WWDG_DeInit(void);
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(uint8_t Counter);
void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F10x_WWDG_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file misc.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "misc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
/** @defgroup MISC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Defines
* @{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**
* @}
*/
/** @defgroup MISC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Functions
* @{
*/
/**
* @brief Configures the priority grouping: pre-emption priority and subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* @retval None
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
/**
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
* the configuration information for the specified NVIC peripheral.
* @retval None
*/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
tmppriority = tmppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
else
{
/* Disable the Selected IRQ Channels -------------------------------------*/
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
}
/**
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
* This parameter can be one of the following values:
* @arg NVIC_VectTab_RAM
* @arg NVIC_VectTab_FLASH
* @param Offset: Vector Table base offset field. This value must be a multiple
* of 0x200.
* @retval None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{
/* Check the parameters */
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
assert_param(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
* This parameter can be one of the following values:
* @arg NVIC_LP_SEVONPEND
* @arg NVIC_LP_SLEEPDEEP
* @arg NVIC_LP_SLEEPONEXIT
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_NVIC_LP(LowPowerMode));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
}
}
/**
* @brief Configures the SysTick clock source.
* @param SysTick_CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_bkp.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the BKP firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_bkp.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup BKP
* @brief BKP driver modules
* @{
*/
/** @defgroup BKP_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_Defines
* @{
*/
/* ------------ BKP registers bit address in the alias region --------------- */
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
/* --- CR Register ----*/
/* Alias word address of TPAL bit */
#define CR_OFFSET (BKP_OFFSET + 0x30)
#define TPAL_BitNumber 0x01
#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
/* Alias word address of TPE bit */
#define TPE_BitNumber 0x00
#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of TPIE bit */
#define CSR_OFFSET (BKP_OFFSET + 0x34)
#define TPIE_BitNumber 0x02
#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
/* Alias word address of TIF bit */
#define TIF_BitNumber 0x09
#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
/* Alias word address of TEF bit */
#define TEF_BitNumber 0x08
#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
/* ---------------------- BKP registers bit mask ------------------------ */
/* RTCCR register bit mask */
#define RTCCR_CAL_MASK ((uint16_t)0xFF80)
#define RTCCR_MASK ((uint16_t)0xFC7F)
/**
* @}
*/
/** @defgroup BKP_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup BKP_Private_Functions
* @{
*/
/**
* @brief Deinitializes the BKP peripheral registers to their default reset values.
* @param None
* @retval None
*/
void BKP_DeInit(void)
{
RCC_BackupResetCmd(ENABLE);
RCC_BackupResetCmd(DISABLE);
}
/**
* @brief Configures the Tamper Pin active level.
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
* This parameter can be one of the following values:
* @arg BKP_TamperPinLevel_High: Tamper pin active on high level
* @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
* @retval None
*/
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
{
/* Check the parameters */
assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
*(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
}
/**
* @brief Enables or disables the Tamper Pin activation.
* @param NewState: new state of the Tamper Pin activation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void BKP_TamperPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Tamper Pin Interrupt.
* @param NewState: new state of the Tamper Pin Interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void BKP_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
}
/**
* @brief Select the RTC output source to output on the Tamper pin.
* @param BKP_RTCOutputSource: specifies the RTC output source.
* This parameter can be one of the following values:
* @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
* @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
* divided by 64 on the Tamper pin.
* @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
* the Tamper pin.
* @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
* the Tamper pin.
* @retval None
*/
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
{
uint16_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
tmpreg = BKP->RTCCR;
/* Clear CCO, ASOE and ASOS bits */
tmpreg &= RTCCR_MASK;
/* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
tmpreg |= BKP_RTCOutputSource;
/* Store the new value */
BKP->RTCCR = tmpreg;
}
/**
* @brief Sets RTC Clock Calibration value.
* @param CalibrationValue: specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x7F.
* @retval None
*/
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
{
uint16_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
tmpreg = BKP->RTCCR;
/* Clear CAL[6:0] bits */
tmpreg &= RTCCR_CAL_MASK;
/* Set CAL[6:0] bits according to CalibrationValue value */
tmpreg |= CalibrationValue;
/* Store the new value */
BKP->RTCCR = tmpreg;
}
/**
* @brief Writes user data to the specified Data Backup Register.
* @param BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42]
* @param Data: data to write
* @retval None
*/
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_BKP_DR(BKP_DR));
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
*(__IO uint32_t *) tmp = Data;
}
/**
* @brief Reads data from the specified Data Backup Register.
* @param BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42]
* @retval The content of the specified Data Backup Register
*/
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_BKP_DR(BKP_DR));
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
return (*(__IO uint16_t *) tmp);
}
/**
* @brief Checks whether the Tamper Pin Event flag is set or not.
* @param None
* @retval The new state of the Tamper Pin Event flag (SET or RESET).
*/
FlagStatus BKP_GetFlagStatus(void)
{
return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
}
/**
* @brief Clears Tamper Pin Event pending flag.
* @param None
* @retval None
*/
void BKP_ClearFlag(void)
{
/* Set CTE bit to clear Tamper Pin Event flag */
BKP->CSR |= BKP_CSR_CTE;
}
/**
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
* @param None
* @retval The new state of the Tamper Pin Interrupt (SET or RESET).
*/
ITStatus BKP_GetITStatus(void)
{
return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
}
/**
* @brief Clears Tamper Pin Interrupt pending bit.
* @param None
* @retval None
*/
void BKP_ClearITPendingBit(void)
{
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
BKP->CSR |= BKP_CSR_CTI;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_cec.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the CEC firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_cec.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup CEC
* @brief CEC driver modules
* @{
*/
/** @defgroup CEC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup CEC_Private_Defines
* @{
*/
/* ------------ CEC registers bit address in the alias region ----------- */
#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
/* --- CFGR Register ---*/
/* Alias word address of PE bit */
#define CFGR_OFFSET (CEC_OFFSET + 0x00)
#define PE_BitNumber 0x00
#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
/* Alias word address of IE bit */
#define IE_BitNumber 0x01
#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of TSOM bit */
#define CSR_OFFSET (CEC_OFFSET + 0x10)
#define TSOM_BitNumber 0x00
#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
/* Alias word address of TEOM bit */
#define TEOM_BitNumber 0x01
#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
/**
* @}
*/
/** @defgroup CEC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CEC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup CEC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup CEC_Private_Functions
* @{
*/
/**
* @brief Deinitializes the CEC peripheral registers to their default reset
* values.
* @param None
* @retval None
*/
void CEC_DeInit(void)
{
/* Enable CEC reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
/* Release CEC from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
}
/**
* @brief Initializes the CEC peripheral according to the specified
* parameters in the CEC_InitStruct.
* @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
* contains the configuration information for the specified
* CEC peripheral.
* @retval None
*/
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
{
uint16_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
/*---------------------------- CEC CFGR Configuration -----------------*/
/* Get the CEC CFGR value */
tmpreg = CEC->CFGR;
/* Clear BTEM and BPEM bits */
tmpreg &= CFGR_CLEAR_Mask;
/* Configure CEC: Bit Timing Error and Bit Period Error */
tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
/* Write to CEC CFGR register*/
CEC->CFGR = tmpreg;
}
/**
* @brief Enables or disables the specified CEC peripheral.
* @param NewState: new state of the CEC peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CEC_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
if(NewState == DISABLE)
{
/* Wait until the PE bit is cleared by hardware (Idle Line detected) */
while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
{
}
}
}
/**
* @brief Enables or disables the CEC interrupt.
* @param NewState: new state of the CEC interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CEC_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
}
/**
* @brief Defines the Own Address of the CEC device.
* @param CEC_OwnAddress: The CEC own address
* @retval None
*/
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
{
/* Check the parameters */
assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
/* Set the CEC own address */
CEC->OAR = CEC_OwnAddress;
}
/**
* @brief Sets the CEC prescaler value.
* @param CEC_Prescaler: CEC prescaler new value
* @retval None
*/
void CEC_SetPrescaler(uint16_t CEC_Prescaler)
{
/* Check the parameters */
assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
/* Set the Prescaler value*/
CEC->PRES = CEC_Prescaler;
}
/**
* @brief Transmits single data through the CEC peripheral.
* @param Data: the data to transmit.
* @retval None
*/
void CEC_SendDataByte(uint8_t Data)
{
/* Transmit Data */
CEC->TXD = Data ;
}
/**
* @brief Returns the most recent received data by the CEC peripheral.
* @param None
* @retval The received data.
*/
uint8_t CEC_ReceiveDataByte(void)
{
/* Receive Data */
return (uint8_t)(CEC->RXD);
}
/**
* @brief Starts a new message.
* @param None
* @retval None
*/
void CEC_StartOfMessage(void)
{
/* Starts of new message */
*(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
}
/**
* @brief Transmits message with or without an EOM bit.
* @param NewState: new state of the CEC Tx End Of Message.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CEC_EndOfMessageCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* The data byte will be transmitted with or without an EOM bit*/
*(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
}
/**
* @brief Gets the CEC flag status
* @param CEC_FLAG: specifies the CEC flag to check.
* This parameter can be one of the following values:
* @arg CEC_FLAG_BTE: Bit Timing Error
* @arg CEC_FLAG_BPE: Bit Period Error
* @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
* @arg CEC_FLAG_SBE: Start Bit Error
* @arg CEC_FLAG_ACKE: Block Acknowledge Error
* @arg CEC_FLAG_LINE: Line Error
* @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
* @arg CEC_FLAG_TEOM: Tx End Of Message
* @arg CEC_FLAG_TERR: Tx Error
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
* @arg CEC_FLAG_RSOM: Rx Start Of Message
* @arg CEC_FLAG_REOM: Rx End Of Message
* @arg CEC_FLAG_RERR: Rx Error
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
* @retval The new state of CEC_FLAG (SET or RESET)
*/
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t cecreg = 0, cecbase = 0;
/* Check the parameters */
assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
/* Get the CEC peripheral base address */
cecbase = (uint32_t)(CEC_BASE);
/* Read flag register index */
cecreg = CEC_FLAG >> 28;
/* Get bit[23:0] of the flag */
CEC_FLAG &= FLAG_Mask;
if(cecreg != 0)
{
/* Flag in CEC ESR Register */
CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
/* Get the CEC ESR register address */
cecbase += 0xC;
}
else
{
/* Get the CEC CSR register address */
cecbase += 0x10;
}
if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
{
/* CEC_FLAG is set */
bitstatus = SET;
}
else
{
/* CEC_FLAG is reset */
bitstatus = RESET;
}
/* Return the CEC_FLAG status */
return bitstatus;
}
/**
* @brief Clears the CEC's pending flags.
* @param CEC_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg CEC_FLAG_TERR: Tx Error
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
* @arg CEC_FLAG_RSOM: Rx Start Of Message
* @arg CEC_FLAG_REOM: Rx End Of Message
* @arg CEC_FLAG_RERR: Rx Error
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
* @retval None
*/
void CEC_ClearFlag(uint32_t CEC_FLAG)
{
uint32_t tmp = 0x0;
/* Check the parameters */
assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
tmp = CEC->CSR & 0x2;
/* Clear the selected CEC flags */
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
}
/**
* @brief Checks whether the specified CEC interrupt has occurred or not.
* @param CEC_IT: specifies the CEC interrupt source to check.
* This parameter can be one of the following values:
* @arg CEC_IT_TERR: Tx Error
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
* @arg CEC_IT_RERR: Rx Error
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
* @retval The new state of CEC_IT (SET or RESET).
*/
ITStatus CEC_GetITStatus(uint8_t CEC_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_CEC_GET_IT(CEC_IT));
/* Get the CEC IT enable bit status */
enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
/* Check the status of the specified CEC interrupt */
if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
{
/* CEC_IT is set */
bitstatus = SET;
}
else
{
/* CEC_IT is reset */
bitstatus = RESET;
}
/* Return the CEC_IT status */
return bitstatus;
}
/**
* @brief Clears the CEC's interrupt pending bits.
* @param CEC_IT: specifies the CEC interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg CEC_IT_TERR: Tx Error
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
* @arg CEC_IT_RERR: Rx Error
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
* @retval None
*/
void CEC_ClearITPendingBit(uint16_t CEC_IT)
{
uint32_t tmp = 0x0;
/* Check the parameters */
assert_param(IS_CEC_GET_IT(CEC_IT));
tmp = CEC->CSR & 0x2;
/* Clear the selected CEC interrupt pending bits */
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_crc.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the CRC firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_crc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
/** @defgroup CRC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup CRC_Private_Functions
* @{
*/
/**
* @brief Resets the CRC Data register (DR).
* @param None
* @retval None
*/
void CRC_ResetDR(void)
{
/* Reset CRC generator */
CRC->CR = CRC_CR_RESET;
}
/**
* @brief Computes the 32-bit CRC of a given data word(32-bit).
* @param Data: data word(32-bit) to compute its CRC
* @retval 32-bit CRC
*/
uint32_t CRC_CalcCRC(uint32_t Data)
{
CRC->DR = Data;
return (CRC->DR);
}
/**
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
* @param pBuffer: pointer to the buffer containing the data to be computed
* @param BufferLength: length of the buffer to be computed
* @retval 32-bit CRC
*/
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DR = pBuffer[index];
}
return (CRC->DR);
}
/**
* @brief Returns the current CRC value.
* @param None
* @retval 32-bit CRC
*/
uint32_t CRC_GetCRC(void)
{
return (CRC->DR);
}
/**
* @brief Stores a 8-bit data in the Independent Data(ID) register.
* @param IDValue: 8-bit value to be stored in the ID register
* @retval None
*/
void CRC_SetIDRegister(uint8_t IDValue)
{
CRC->IDR = IDValue;
}
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
* @param None
* @retval 8-bit value of the ID register
*/
uint8_t CRC_GetIDRegister(void)
{
return (CRC->IDR);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_dac.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the DAC firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dac.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
/** @defgroup DAC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Defines
* @{
*/
/* CR register Mask */
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
/* DOR register offset */
#define DOR_OFFSET ((uint32_t)0x0000002C)
/**
* @}
*/
/** @defgroup DAC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DAC_Private_Functions
* @{
*/
/**
* @brief Deinitializes the DAC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void DAC_DeInit(void)
{
/* Enable DAC reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
/* Release DAC from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
}
/**
* @brief Initializes the DAC peripheral according to the specified
* parameters in the DAC_InitStruct.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
* contains the configuration information for the specified DAC channel.
* @retval None
*/
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
/*---------------------------- DAC CR Configuration --------------------------*/
/* Get the DAC CR value */
tmpreg1 = DAC->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
mask/amplitude for wave generation */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set WAVEx bits according to DAC_WaveGeneration value */
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << DAC_Channel;
/* Write to DAC CR */
DAC->CR = tmpreg1;
}
/**
* @brief Fills each DAC_InitStruct member with its default value.
* @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
{
/*--------------- Reset DAC init structure parameters values -----------------*/
/* Initialize the DAC_Trigger member */
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
/* Initialize the DAC_WaveGeneration member */
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
/* Initialize the DAC_OutputBuffer member */
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
}
/**
* @brief Enables or disables the specified DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel */
DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
}
}
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/**
* @brief Enables or disables the specified DAC interrupts.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @param NewState: new state of the specified DAC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_DAC_IT(DAC_IT));
if (NewState != DISABLE)
{
/* Enable the selected DAC interrupts */
DAC->CR |= (DAC_IT << DAC_Channel);
}
else
{
/* Disable the selected DAC interrupts */
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
}
}
#endif
/**
* @brief Enables or disables the specified DAC channel DMA request.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel DMA request */
DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
}
}
/**
* @brief Enables or disables the selected DAC channel software trigger.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
}
else
{
/* Disable software trigger for the selected DAC channel */
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
}
}
/**
* @brief Enables or disables simultaneously the two DAC channels software
* triggers.
* @param NewState: new state of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
}
else
{
/* Disable software trigger for both DAC channels */
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
}
}
/**
* @brief Enables or disables the selected DAC channel wave generation.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_Wave: Specifies the wave type to enable or disable.
* This parameter can be one of the following values:
* @arg DAC_Wave_Noise: noise wave generation
* @arg DAC_Wave_Triangle: triangle wave generation
* @param NewState: new state of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_WAVE(DAC_Wave));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected wave generation for the selected DAC channel */
DAC->CR |= DAC_Wave << DAC_Channel;
}
else
{
/* Disable the selected wave generation for the selected DAC channel */
DAC->CR &= ~(DAC_Wave << DAC_Channel);
}
}
/**
* @brief Set the specified data holding register value for DAC channel1.
* @param DAC_Align: Specifies the data alignment for DAC channel1.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R1_OFFSET + DAC_Align;
/* Set the DAC channel1 selected data holding register */
*(__IO uint32_t *) tmp = Data;
}
/**
* @brief Set the specified data holding register value for DAC channel2.
* @param DAC_Align: Specifies the data alignment for DAC channel2.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R2_OFFSET + DAC_Align;
/* Set the DAC channel2 selected data holding register */
*(__IO uint32_t *)tmp = Data;
}
/**
* @brief Set the specified data holding register value for dual channel
* DAC.
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
* holding register.
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
* holding register.
* @retval None
*/
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
{
uint32_t data = 0, tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (DAC_Align == DAC_Align_8b_R)
{
data = ((uint32_t)Data2 << 8) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16) | Data1;
}
tmp = (uint32_t)DAC_BASE;
tmp += DHR12RD_OFFSET + DAC_Align;
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
}
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
tmp = (uint32_t) DAC_BASE ;
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
/* Returns the DAC channel data output register value */
return (uint16_t) (*(__IO uint32_t*) tmp);
}
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
/**
* @brief Checks whether the specified DAC flag is set or not.
* @param DAC_Channel: thee selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to check.
* This parameter can be only of the following value:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @retval The new state of DAC_FLAG (SET or RESET).
*/
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* Check the status of the specified DAC flag */
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
{
/* DAC_FLAG is set */
bitstatus = SET;
}
else
{
/* DAC_FLAG is reset */
bitstatus = RESET;
}
/* Return the DAC_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DAC channelx's pending flags.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to clear.
* This parameter can be of the following value:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @retval None
*/
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* Clear the selected DAC flags */
DAC->SR = (DAC_FLAG << DAC_Channel);
}
/**
* @brief Checks whether the specified DAC interrupt has occurred or not.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt source to check.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @retval The new state of DAC_IT (SET or RESET).
*/
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Get the DAC_IT enable bit status */
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
/* Check the status of the specified DAC interrupt */
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
{
/* DAC_IT is set */
bitstatus = SET;
}
else
{
/* DAC_IT is reset */
bitstatus = RESET;
}
/* Return the DAC_IT status */
return bitstatus;
}
/**
* @brief Clears the DAC channelx's interrupt pending bits.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @retval None
*/
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Clear the selected DAC interrupt pending bits */
DAC->SR = (DAC_IT << DAC_Channel);
}
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

162
FWLIB/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c Normal file
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/**
******************************************************************************
* @file stm32f10x_dbgmcu.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the DBGMCU firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dbgmcu.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup DBGMCU
* @brief DBGMCU driver modules
* @{
*/
/** @defgroup DBGMCU_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Defines
* @{
*/
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/**
* @}
*/
/** @defgroup DBGMCU_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DBGMCU_Private_Functions
* @{
*/
/**
* @brief Returns the device revision identifier.
* @param None
* @retval Device revision identifier
*/
uint32_t DBGMCU_GetREVID(void)
{
return(DBGMCU->IDCODE >> 16);
}
/**
* @brief Returns the device identifier.
* @param None
* @retval Device identifier
*/
uint32_t DBGMCU_GetDEVID(void)
{
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
}
/**
* @brief Configures the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
* @param DBGMCU_Periph: specifies the peripheral and low power mode.
* This parameter can be any combination of the following values:
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
* @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
* @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
* @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
* @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
* @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
* @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
* @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
* @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
* @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
* @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
* @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
* @param NewState: new state of the specified peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->CR |= DBGMCU_Periph;
}
else
{
DBGMCU->CR &= ~DBGMCU_Periph;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

714
FWLIB/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c Normal file
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/**
******************************************************************************
* @file stm32f10x_dma.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the DMA firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_dma.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
/** @defgroup DMA_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_Defines
* @{
*/
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
/* DMA2 Channelx interrupt pending bit masks */
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
/* DMA2 FLAG mask */
#define FLAG_Mask ((uint32_t)0x10000000)
/* DMA registers Masks */
#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
/**
* @}
*/
/** @defgroup DMA_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_Functions
* @{
*/
/**
* @brief Deinitializes the DMAy Channelx registers to their default reset
* values.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval None
*/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
/* Reset DMAy Channelx control register */
DMAy_Channelx->CCR = 0;
/* Reset DMAy Channelx remaining bytes register */
DMAy_Channelx->CNDTR = 0;
/* Reset DMAy Channelx peripheral address register */
DMAy_Channelx->CPAR = 0;
/* Reset DMAy Channelx memory address register */
DMAy_Channelx->CMAR = 0;
if (DMAy_Channelx == DMA1_Channel1)
{
/* Reset interrupt pending bits for DMA1 Channel1 */
DMA1->IFCR |= DMA1_Channel1_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel2)
{
/* Reset interrupt pending bits for DMA1 Channel2 */
DMA1->IFCR |= DMA1_Channel2_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel3)
{
/* Reset interrupt pending bits for DMA1 Channel3 */
DMA1->IFCR |= DMA1_Channel3_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel4)
{
/* Reset interrupt pending bits for DMA1 Channel4 */
DMA1->IFCR |= DMA1_Channel4_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel5)
{
/* Reset interrupt pending bits for DMA1 Channel5 */
DMA1->IFCR |= DMA1_Channel5_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel6)
{
/* Reset interrupt pending bits for DMA1 Channel6 */
DMA1->IFCR |= DMA1_Channel6_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel7)
{
/* Reset interrupt pending bits for DMA1 Channel7 */
DMA1->IFCR |= DMA1_Channel7_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel1)
{
/* Reset interrupt pending bits for DMA2 Channel1 */
DMA2->IFCR |= DMA2_Channel1_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel2)
{
/* Reset interrupt pending bits for DMA2 Channel2 */
DMA2->IFCR |= DMA2_Channel2_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel3)
{
/* Reset interrupt pending bits for DMA2 Channel3 */
DMA2->IFCR |= DMA2_Channel3_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel4)
{
/* Reset interrupt pending bits for DMA2 Channel4 */
DMA2->IFCR |= DMA2_Channel4_IT_Mask;
}
else
{
if (DMAy_Channelx == DMA2_Channel5)
{
/* Reset interrupt pending bits for DMA2 Channel5 */
DMA2->IFCR |= DMA2_Channel5_IT_Mask;
}
}
}
/**
* @brief Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
* contains the configuration information for the specified DMA Channel.
* @retval None
*/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
/* Get the DMAy_Channelx CCR value */
tmpreg = DMAy_Channelx->CCR;
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmpreg &= CCR_CLEAR_Mask;
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
/* Set DIR bit according to DMA_DIR value */
/* Set CIRC bit according to DMA_Mode value */
/* Set PINC bit according to DMA_PeripheralInc value */
/* Set MINC bit according to DMA_MemoryInc value */
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
/* Set MSIZE bits according to DMA_MemoryDataSize value */
/* Set PL bits according to DMA_Priority value */
/* Set the MEM2MEM bit according to DMA_M2M value */
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
/* Write to DMAy Channelx CCR */
DMAy_Channelx->CCR = tmpreg;
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
/* Write to DMAy Channelx CPAR */
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
/* Write to DMAy Channelx CMAR */
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
}
/**
* @brief Fills each DMA_InitStruct member with its default value.
* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
{
/*-------------- Reset DMA init structure parameters values ------------------*/
/* Initialize the DMA_PeripheralBaseAddr member */
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
/* Initialize the DMA_MemoryBaseAddr member */
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
/* Initialize the DMA_DIR member */
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
/* Initialize the DMA_BufferSize member */
DMA_InitStruct->DMA_BufferSize = 0;
/* Initialize the DMA_PeripheralInc member */
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
/* Initialize the DMA_MemoryInc member */
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
/* Initialize the DMA_PeripheralDataSize member */
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
/* Initialize the DMA_MemoryDataSize member */
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
/* Initialize the DMA_Mode member */
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
/* Initialize the DMA_Priority member */
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
/* Initialize the DMA_M2M member */
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
}
/**
* @brief Enables or disables the specified DMAy Channelx.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param NewState: new state of the DMAy Channelx.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMAy Channelx */
DMAy_Channelx->CCR |= DMA_CCR1_EN;
}
else
{
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
}
}
/**
* @brief Enables or disables the specified DMAy Channelx interrupts.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
* or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @param NewState: new state of the specified DMA interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA interrupts */
DMAy_Channelx->CCR |= DMA_IT;
}
else
{
/* Disable the selected DMA interrupts */
DMAy_Channelx->CCR &= ~DMA_IT;
}
}
/**
* @brief Sets the number of data units in the current DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DataNumber: The number of data units in the current DMAy Channelx
* transfer.
* @note This function can only be used when the DMAy_Channelx is disabled.
* @retval None.
*/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DataNumber;
}
/**
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval The number of remaining data units in the current DMAy Channelx
* transfer.
*/
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Return the number of remaining data units for DMAy Channelx */
return ((uint16_t)(DMAy_Channelx->CNDTR));
}
/**
* @brief Checks whether the specified DMAy Channelx flag is set or not.
* @param DMAy_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
* @retval The new state of DMAy_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
/* Calculate the used DMAy */
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR ;
}
else
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR ;
}
/* Check the status of the specified DMAy flag */
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
{
/* DMAy_FLAG is set */
bitstatus = SET;
}
else
{
/* DMAy_FLAG is reset */
bitstatus = RESET;
}
/* Return the DMAy_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx's pending flags.
* @param DMAy_FLAG: specifies the flag to clear.
* This parameter can be any combination (for the same DMA) of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
* @retval None
*/
void DMA_ClearFlag(uint32_t DMAy_FLAG)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
/* Calculate the used DMAy */
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
{
/* Clear the selected DMAy flags */
DMA2->IFCR = DMAy_FLAG;
}
else
{
/* Clear the selected DMAy flags */
DMA1->IFCR = DMAy_FLAG;
}
}
/**
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
* @param DMAy_IT: specifies the DMAy interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
* @retval The new state of DMAy_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_IT(DMAy_IT));
/* Calculate the used DMA */
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR;
}
else
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR;
}
/* Check the status of the specified DMAy interrupt */
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
{
/* DMAy_IT is set */
bitstatus = SET;
}
else
{
/* DMAy_IT is reset */
bitstatus = RESET;
}
/* Return the DMA_IT status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx's interrupt pending bits.
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
* @retval None
*/
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
/* Calculate the used DMAy */
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
{
/* Clear the selected DMAy interrupt pending bits */
DMA2->IFCR = DMAy_IT;
}
else
{
/* Clear the selected DMAy interrupt pending bits */
DMA1->IFCR = DMAy_IT;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

269
FWLIB/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c Normal file
View File

@@ -0,0 +1,269 @@
/**
******************************************************************************
* @file stm32f10x_exti.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the EXTI firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_exti.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup EXTI
* @brief EXTI driver modules
* @{
*/
/** @defgroup EXTI_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_Defines
* @{
*/
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
/**
* @}
*/
/** @defgroup EXTI_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_Functions
* @{
*/
/**
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
* @param None
* @retval None
*/
void EXTI_DeInit(void)
{
EXTI->IMR = 0x00000000;
EXTI->EMR = 0x00000000;
EXTI->RTSR = 0x00000000;
EXTI->FTSR = 0x00000000;
EXTI->PR = 0x000FFFFF;
}
/**
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* that contains the configuration information for the EXTI peripheral.
* @retval None
*/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
tmp = (uint32_t)EXTI_BASE;
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
/* Clear EXTI line configuration */
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
/* Select the trigger for the selected external interrupts */
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
/* Rising Falling edge */
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
}
else
{
tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Trigger;
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
}
}
else
{
tmp += EXTI_InitStruct->EXTI_Mode;
/* Disable the selected external lines */
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
}
}
/**
* @brief Fills each EXTI_InitStruct member with its reset value.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/**
* @brief Generates a Software interrupt.
* @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
* @retval None
*/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->SWIER |= EXTI_Line;
}
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param EXTI_Line: specifies the EXTI line flag to check.
* This parameter can be:
* @arg EXTI_Linex: External interrupt line x where x(0..19)
* @retval The new state of EXTI_Line (SET or RESET).
*/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI's line pending flags.
* @param EXTI_Line: specifies the EXTI lines flags to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
* @retval None
*/
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param EXTI_Line: specifies the EXTI line to check.
* This parameter can be:
* @arg EXTI_Linex: External interrupt line x where x(0..19)
* @retval The new state of EXTI_Line (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
enablestatus = EXTI->IMR & EXTI_Line;
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI's line pending bits.
* @param EXTI_Line: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
* @retval None
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f10x_fsmc.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the FSMC firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_fsmc.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup FSMC
* @brief FSMC driver modules
* @{
*/
/** @defgroup FSMC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup FSMC_Private_Defines
* @{
*/
/* --------------------- FSMC registers bit mask ---------------------------- */
/* FSMC BCRx Mask */
#define BCR_MBKEN_Set ((uint32_t)0x00000001)
#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
#define BCR_FACCEN_Set ((uint32_t)0x00000040)
/* FSMC PCRx Mask */
#define PCR_PBKEN_Set ((uint32_t)0x00000004)
#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
#define PCR_ECCEN_Set ((uint32_t)0x00000040)
#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
/**
* @}
*/
/** @defgroup FSMC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup FSMC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup FSMC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup FSMC_Private_Functions
* @{
*/
/**
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
* reset values.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
* @retval None
*/
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
{
/* Check the parameter */
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
/* FSMC_Bank1_NORSRAM1 */
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
{
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
}
/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
else
{
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
}
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
}
/**
* @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @retval None
*/
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
{
/* Check the parameter */
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
/* Set the FSMC_Bank2 registers to their reset values */
FSMC_Bank2->PCR2 = 0x00000018;
FSMC_Bank2->SR2 = 0x00000040;
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
}
/* FSMC_Bank3_NAND */
else
{
/* Set the FSMC_Bank3 registers to their reset values */
FSMC_Bank3->PCR3 = 0x00000018;
FSMC_Bank3->SR3 = 0x00000040;
FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
FSMC_Bank3->PATT3 = 0xFCFCFCFC;
}
}
/**
* @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
* @param None
* @retval None
*/
void FSMC_PCCARDDeInit(void)
{
/* Set the FSMC_Bank4 registers to their reset values */
FSMC_Bank4->PCR4 = 0x00000018;
FSMC_Bank4->SR4 = 0x00000000;
FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
FSMC_Bank4->PATT4 = 0xFCFCFCFC;
FSMC_Bank4->PIO4 = 0xFCFCFCFC;
}
/**
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
* parameters in the FSMC_NORSRAMInitStruct.
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
* structure that contains the configuration information for
* the FSMC NOR/SRAM specified Banks.
* @retval None
*/
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
/* Bank1 NOR/SRAM control register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
}
/* Bank1 NOR/SRAM timing register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
{
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
}
else
{
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
}
}
/**
* @brief Initializes the FSMC NAND Banks according to the specified
* parameters in the FSMC_NANDInitStruct.
* @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
* structure that contains the configuration information for the FSMC
* NAND specified Banks.
* @retval None
*/
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
{
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
/* Check the parameters */
assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
/* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
PCR_MemoryType_NAND |
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
FSMC_NANDInitStruct->FSMC_ECC |
FSMC_NANDInitStruct->FSMC_ECCPageSize |
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
/* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
/* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
{
/* FSMC_Bank2_NAND registers configuration */
FSMC_Bank2->PCR2 = tmppcr;
FSMC_Bank2->PMEM2 = tmppmem;
FSMC_Bank2->PATT2 = tmppatt;
}
else
{
/* FSMC_Bank3_NAND registers configuration */
FSMC_Bank3->PCR3 = tmppcr;
FSMC_Bank3->PMEM3 = tmppmem;
FSMC_Bank3->PATT3 = tmppatt;
}
}
/**
* @brief Initializes the FSMC PCCARD Bank according to the specified
* parameters in the FSMC_PCCARDInitStruct.
* @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
* structure that contains the configuration information for the FSMC
* PCCARD Bank.
* @retval None
*/
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
{
/* Check the parameters */
assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
/* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
FSMC_MemoryDataWidth_16b |
(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
(FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
/* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
/* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
/* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
}
/**
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
* structure which will be initialized.
* @retval None
*/
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* Reset NOR/SRAM Init structure parameters values */
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
}
/**
* @brief Fills each FSMC_NANDInitStruct member with its default value.
* @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
* structure which will be initialized.
* @retval None
*/
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
{
/* Reset NAND Init structure parameters values */
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
}
/**
* @brief Fills each FSMC_PCCARDInitStruct member with its default value.
* @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
* structure which will be initialized.
* @retval None
*/
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
{
/* Reset PCCARD Init structure parameters values */
FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
}
/**
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
}
else
{
/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
}
}
/**
* @brief Enables or disables the specified NAND Memory Bank.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
}
else
{
FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
}
}
else
{
/* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
}
else
{
FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
}
}
}
/**
* @brief Enables or disables the PCCARD Memory Bank.
* @param NewState: new state of the PCCARD Memory Bank.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_PCCARDCmd(FunctionalState NewState)
{
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
}
else
{
/* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
}
}
/**
* @brief Enables or disables the FSMC NAND ECC feature.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @param NewState: new state of the FSMC NAND ECC feature.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
}
else
{
FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
}
}
else
{
/* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
}
else
{
FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
}
}
}
/**
* @brief Returns the error correction code register value.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @retval The Error Correction Code (ECC) value.
*/
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
{
uint32_t eccval = 0x00000000;
if(FSMC_Bank == FSMC_Bank2_NAND)
{
/* Get the ECCR2 register value */
eccval = FSMC_Bank2->ECCR2;
}
else
{
/* Get the ECCR3 register value */
eccval = FSMC_Bank3->ECCR3;
}
/* Return the error correction code value */
return(eccval);
}
/**
* @brief Enables or disables the specified FSMC interrupts.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
* @arg FSMC_IT_Level: Level edge detection interrupt.
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
* @param NewState: new state of the specified FSMC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
{
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
assert_param(IS_FSMC_IT(FSMC_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected FSMC_Bank2 interrupts */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 |= FSMC_IT;
}
/* Enable the selected FSMC_Bank3 interrupts */
else if (FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 |= FSMC_IT;
}
/* Enable the selected FSMC_Bank4 interrupts */
else
{
FSMC_Bank4->SR4 |= FSMC_IT;
}
}
else
{
/* Disable the selected FSMC_Bank2 interrupts */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
}
/* Disable the selected FSMC_Bank3 interrupts */
else if (FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
}
/* Disable the selected FSMC_Bank4 interrupts */
else
{
FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
}
}
}
/**
* @brief Checks whether the specified FSMC flag is set or not.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* @param FSMC_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
* @arg FSMC_FLAG_Level: Level detection Flag.
* @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
* @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
* @retval The new state of FSMC_FLAG (SET or RESET).
*/
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpsr = 0x00000000;
/* Check the parameters */
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
tmpsr = FSMC_Bank2->SR2;
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
tmpsr = FSMC_Bank3->SR3;
}
/* FSMC_Bank4_PCCARD*/
else
{
tmpsr = FSMC_Bank4->SR4;
}
/* Get the flag status */
if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @brief Clears the FSMC's pending flags.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* @param FSMC_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
* @arg FSMC_FLAG_Level: Level detection Flag.
* @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
* @retval None
*/
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
{
/* Check the parameters */
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= ~FSMC_FLAG;
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 &= ~FSMC_FLAG;
}
/* FSMC_Bank4_PCCARD*/
else
{
FSMC_Bank4->SR4 &= ~FSMC_FLAG;
}
}
/**
* @brief Checks whether the specified FSMC interrupt has occurred or not.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* @param FSMC_IT: specifies the FSMC interrupt source to check.
* This parameter can be one of the following values:
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
* @arg FSMC_IT_Level: Level edge detection interrupt.
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
* @retval The new state of FSMC_IT (SET or RESET).
*/
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
/* Check the parameters */
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
assert_param(IS_FSMC_GET_IT(FSMC_IT));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
tmpsr = FSMC_Bank2->SR2;
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
tmpsr = FSMC_Bank3->SR3;
}
/* FSMC_Bank4_PCCARD*/
else
{
tmpsr = FSMC_Bank4->SR4;
}
itstatus = tmpsr & FSMC_IT;
itenable = tmpsr & (FSMC_IT >> 3);
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the FSMC's interrupt pending bits.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* @param FSMC_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
* @arg FSMC_IT_Level: Level edge detection interrupt.
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
* @retval None
*/
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
{
/* Check the parameters */
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
assert_param(IS_FSMC_IT(FSMC_IT));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
}
/* FSMC_Bank4_PCCARD*/
else
{
FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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FWLIB/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c Normal file
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@@ -0,0 +1,650 @@
/**
******************************************************************************
* @file stm32f10x_gpio.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the GPIO firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_gpio.h"
#include "stm32f10x_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
/** @defgroup GPIO_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Private_Defines
* @{
*/
/* ------------ RCC registers bit address in the alias region ----------------*/
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
/* --- EVENTCR Register -----*/
/* Alias word address of EVOE bit */
#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
#define EVOE_BitNumber ((uint8_t)0x07)
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
/* --- MAPR Register ---*/
/* Alias word address of MII_RMII_SEL bit */
#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
#define MII_RMII_SEL_BitNumber ((u8)0x17)
#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
#define LSB_MASK ((uint16_t)0xFFFF)
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
/**
* @}
*/
/** @defgroup GPIO_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Private_Functions
* @{
*/
/**
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @retval None
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
if (GPIOx == GPIOA)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
}
else if (GPIOx == GPIOB)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
}
else if (GPIOx == GPIOC)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
}
else if (GPIOx == GPIOD)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
}
else if (GPIOx == GPIOE)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
}
else if (GPIOx == GPIOF)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
}
else
{
if (GPIOx == GPIOG)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
}
}
}
/**
* @brief Deinitializes the Alternate Functions (remap, event control
* and EXTI configuration) registers to their default reset values.
* @param None
* @retval None
*/
void GPIO_AFIODeInit(void)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
}
/**
* @brief Initializes the GPIOx peripheral according to the specified
* parameters in the GPIO_InitStruct.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO peripheral.
* @retval None
*/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
uint32_t tmpreg = 0x00, pinmask = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
/*---------------------------- GPIO Mode Configuration -----------------------*/
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
{
/* Check the parameters */
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
/* Output mode */
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
}
/*---------------------------- GPIO CRL Configuration ------------------------*/
/* Configure the eight low port pins */
if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
{
tmpreg = GPIOx->CRL;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
/* Get the port pins position */
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding low control register bits */
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((uint32_t)0x01) << pinpos);
}
else
{
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
}
}
}
}
GPIOx->CRL = tmpreg;
}
/*---------------------------- GPIO CRH Configuration ------------------------*/
/* Configure the eight high port pins */
if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
{
tmpreg = GPIOx->CRH;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = (((uint32_t)0x01) << (pinpos + 0x08));
/* Get the port pins position */
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding high control register bits */
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
}
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
}
}
}
GPIOx->CRH = tmpreg;
}
}
/**
* @brief Fills each GPIO_InitStruct member with its default value.
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval The input port pin value.
*/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified GPIO input data port.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @retval GPIO input data port value.
*/
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->IDR);
}
/**
* @brief Reads the specified output data port bit.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval The output port pin value.
*/
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified GPIO output data port.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @retval GPIO output data port value.
*/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->ODR);
}
/**
* @brief Sets the selected data port bits.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BSRR = GPIO_Pin;
}
/**
* @brief Clears the selected data port bits.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BRR = GPIO_Pin;
}
/**
* @brief Sets or clears the selected data port bit.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* @param BitVal: specifies the value to be written to the selected bit.
* This parameter can be one of the BitAction enum values:
* @arg Bit_RESET: to clear the port pin
* @arg Bit_SET: to set the port pin
* @retval None
*/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_BIT_ACTION(BitVal));
if (BitVal != Bit_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BRR = GPIO_Pin;
}
}
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param PortVal: specifies the value to be written to the port output data register.
* @retval None
*/
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->ODR = PortVal;
}
/**
* @brief Locks GPIO Pins configuration registers.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp = 0x00010000;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
tmp |= GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Reset LCKK bit */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
}
/**
* @brief Selects the GPIO pin used as Event output.
* @param GPIO_PortSource: selects the GPIO port to be used as source
* for Event output.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
* @param GPIO_PinSource: specifies the pin for the Event output.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* @retval None
*/
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
{
uint32_t tmpreg = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
tmpreg = AFIO->EVCR;
/* Clear the PORT[6:4] and PIN[3:0] bits */
tmpreg &= EVCR_PORTPINCONFIG_MASK;
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
tmpreg |= GPIO_PinSource;
AFIO->EVCR = tmpreg;
}
/**
* @brief Enables or disables the Event Output.
* @param NewState: new state of the Event output.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void GPIO_EventOutputCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
}
/**
* @brief Changes the mapping of the specified pin.
* @param GPIO_Remap: selects the pin to remap.
* This parameter can be one of the following values:
* @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
* @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
* @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping
* @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping
* @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
* @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
* @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
* @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
* @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
* @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
* @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
* @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
* @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
* @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
* @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
* @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
* @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping
* @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
* @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
* @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
* @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
* @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
* @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
* @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
* @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
* @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
* @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
* @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
* When the SPI3/I2S3 is remapped using this function, the SWJ is configured
* to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
* @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
* to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
* If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
* Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
* @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
* @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
* @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
* @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
* @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
* @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
* @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
* @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
* @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
* @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
* @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
* @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
* @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
* @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
* @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
* only for High density Value line devices)
* @param NewState: new state of the port pin remapping.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
{
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_REMAP(GPIO_Remap));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if((GPIO_Remap & 0x80000000) == 0x80000000)
{
tmpreg = AFIO->MAPR2;
}
else
{
tmpreg = AFIO->MAPR;
}
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
tmp = GPIO_Remap & LSB_MASK;
if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
{
tmpreg &= DBGAFR_SWJCFG_MASK;
AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
}
else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
{
tmp1 = ((uint32_t)0x03) << tmpmask;
tmpreg &= ~tmp1;
tmpreg |= ~DBGAFR_SWJCFG_MASK;
}
else
{
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
tmpreg |= ~DBGAFR_SWJCFG_MASK;
}
if (NewState != DISABLE)
{
tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
}
if((GPIO_Remap & 0x80000000) == 0x80000000)
{
AFIO->MAPR2 = tmpreg;
}
else
{
AFIO->MAPR = tmpreg;
}
}
/**
* @brief Selects the GPIO pin used as EXTI Line.
* @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
* @param GPIO_PinSource: specifies the EXTI line to be configured.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* @retval None
*/
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
{
uint32_t tmp = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
}
/**
* @brief Selects the Ethernet media interface.
* @note This function applies only to STM32 Connectivity line devices.
* @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
* This parameter can be one of the following values:
* @arg GPIO_ETH_MediaInterface_MII: MII mode
* @arg GPIO_ETH_MediaInterface_RMII: RMII mode
* @retval None
*/
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
{
assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
/* Configure MII_RMII selection bit */
*(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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