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Backup before error handling refactoring

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jkwoo
2026-07-13 17:10:02 +09:00
commit 04fc19b485
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USER/FLASH/lst/BMU_21S_APP.map Normal file
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ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
2 00000000 ; uC/CPU
3 00000000 ; CPU CONFIGURATION &
PORT LAYER
4 00000000 ;
5 00000000 ; (c) Copyright 2004-2011; Micr
ium, Inc.; Weston, FL
6 00000000 ;
7 00000000 ; All rights reserved. Protected by inter
national copyright laws.
8 00000000 ;
9 00000000 ; uC/CPU is provided in source form to reg
istered licensees ONLY. It is
10 00000000 ; illegal to distribute this source code t
o any third party unless you receive
11 00000000 ; written permission by an authorized Micr
ium representative. Knowledge of
12 00000000 ; the source code may NOT be used to devel
op a similar product.
13 00000000 ;
14 00000000 ; Please help us continue to provide the E
mbedded community with the finest
15 00000000 ; software available. Your honesty is gre
atly appreciated.
16 00000000 ;
17 00000000 ; You can contact us at www.micrium.com.
18 00000000 ;*******************************************************
*************************************************
19 00000000
20 00000000 ;*******************************************************
*************************************************
21 00000000 ;
22 00000000 ; CPU PORT FI
LE
23 00000000 ;
24 00000000 ; ARM-Cortex-
M3
25 00000000 ; RealView Developm
ent Suite
26 00000000 ; RealView Microcontroller De
velopment Kit (MDK)
27 00000000 ; ARM Developer Su
ite (ADS)
28 00000000 ; Keil uVisio
n
29 00000000 ;
30 00000000 ; Filename : cpu_a.asm
31 00000000 ; Version : V1.29.01.00
32 00000000 ; Programmer(s) : BAN
33 00000000 ;*******************************************************
*************************************************
34 00000000
35 00000000
36 00000000 ;*******************************************************
*************************************************
37 00000000 ; PUBLIC FUNCT
IONS
38 00000000 ;*******************************************************
ARM Macro Assembler Page 2
*************************************************
39 00000000
40 00000000 EXPORT CPU_IntDis
41 00000000 EXPORT CPU_IntEn
42 00000000
43 00000000 EXPORT CPU_SR_Save
44 00000000 EXPORT CPU_SR_Restore
45 00000000
46 00000000 EXPORT CPU_WaitForInt
47 00000000 EXPORT CPU_WaitForExcept
48 00000000
49 00000000
50 00000000 EXPORT CPU_CntLeadZeros
51 00000000 EXPORT CPU_CntTrailZeros
52 00000000 EXPORT CPU_RevBits
53 00000000
54 00000000
55 00000000 ;*******************************************************
*************************************************
56 00000000 ; CODE GENERATION D
IRECTIVES
57 00000000 ;*******************************************************
*************************************************
58 00000000
59 00000000 AREA |.text|, CODE, READONLY, ALIGN=
2
60 00000000 THUMB
61 00000000 REQUIRE8
62 00000000 PRESERVE8
63 00000000
64 00000000
65 00000000 ;$PAGE
66 00000000 ;*******************************************************
*************************************************
67 00000000 ; DISABLE and ENABLE
INTERRUPTS
68 00000000 ;
69 00000000 ; Description : Disable/Enable interrupts.
70 00000000 ;
71 00000000 ; Prototypes : void CPU_IntDis(void);
72 00000000 ; void CPU_IntEn (void);
73 00000000 ;*******************************************************
*************************************************
74 00000000
75 00000000 CPU_IntDis
76 00000000 B672 CPSID I
77 00000002 4770 BX LR
78 00000004
79 00000004
80 00000004 CPU_IntEn
81 00000004 B662 CPSIE I
82 00000006 4770 BX LR
83 00000008
84 00000008
85 00000008 ;*******************************************************
*************************************************
86 00000008 ; CRITICAL SECTION
FUNCTIONS
87 00000008 ;
ARM Macro Assembler Page 3
88 00000008 ; Description : Disable/Enable interrupts by preserving
the state of interrupts. Generally speaking, the
89 00000008 ; state of the interrupt disable flag is s
tored in the local variable 'cpu_sr' & interrupts
90 00000008 ; are then disabled ('cpu_sr' is allocated
in all functions that need to disable interrupts).
91 00000008 ; The previous interrupt state is restored
by copying 'cpu_sr' into the CPU's status register.
92 00000008 ;
93 00000008 ; Prototypes : CPU_SR CPU_SR_Save (void);
94 00000008 ; void CPU_SR_Restore(CPU_SR cpu_sr);
95 00000008 ;
96 00000008 ; Note(s) : (1) These functions are used in general
like this :
97 00000008 ;
98 00000008 ; void Task (void *p_arg)
99 00000008 ; {
100 00000008 ; CPU_SR_ALLOC();
/* Allocate storage for CPU status register */
101 00000008 ; :
102 00000008 ; :
103 00000008 ; CPU_CRITICAL_ENTER();
/* cpu_sr = CPU_SR_Save(); */
104 00000008 ; :
105 00000008 ; :
106 00000008 ; CPU_CRITICAL_EXIT();
/* CPU_SR_Restore(cpu_sr); */
107 00000008 ; :
108 00000008 ; }
109 00000008 ;*******************************************************
*************************************************
110 00000008
111 00000008 CPU_SR_Save
112 00000008 F3EF 8010 MRS R0, PRIMASK ; Set prio int mask
to mask all (excep
t faults)
113 0000000C B672 CPSID I
114 0000000E 4770 BX LR
115 00000010
116 00000010
117 00000010 CPU_SR_Restore ; See Note #2.
118 00000010 F380 8810 MSR PRIMASK, R0
119 00000014 4770 BX LR
120 00000016
121 00000016
122 00000016 ;$PAGE
123 00000016 ;*******************************************************
*************************************************
124 00000016 ; WAIT FOR INTER
RUPT
125 00000016 ;
126 00000016 ; Description : Enters sleep state, which will be exited
when an interrupt is received.
127 00000016 ;
128 00000016 ; Prototypes : void CPU_WaitForInt (void)
129 00000016 ;
130 00000016 ; Argument(s) : none.
131 00000016 ;*******************************************************
*************************************************
ARM Macro Assembler Page 4
132 00000016
133 00000016 CPU_WaitForInt
134 00000016 BF30 WFI ; Wait for interrup
t
135 00000018 4770 BX LR
136 0000001A
137 0000001A
138 0000001A ;*******************************************************
*************************************************
139 0000001A ; WAIT FOR EXCEP
TION
140 0000001A ;
141 0000001A ; Description : Enters sleep state, which will be exited
when an exception is received.
142 0000001A ;
143 0000001A ; Prototypes : void CPU_WaitForExcept (void)
144 0000001A ;
145 0000001A ; Argument(s) : none.
146 0000001A ;*******************************************************
*************************************************
147 0000001A
148 0000001A CPU_WaitForExcept
149 0000001A BF20 WFE ; Wait for exceptio
n
150 0000001C 4770 BX LR
151 0000001E
152 0000001E
153 0000001E ;$PAGE
154 0000001E ;*******************************************************
*************************************************
155 0000001E ; CPU_CntLeadZer
os()
156 0000001E ; COUNT LEADING Z
EROS
157 0000001E ;
158 0000001E ; Description : Counts the number of contiguous, most-si
gnificant, leading zero bits before the
159 0000001E ; first binary one bit in a data value
.
160 0000001E ;
161 0000001E ; Prototype : CPU_DATA CPU_CntLeadZeros(CPU_DATA val
);
162 0000001E ;
163 0000001E ; Argument(s) : val Data value to count leading
zero bits.
164 0000001E ;
165 0000001E ; Return(s) : Number of contiguous, most-significant,
leading zero bits in 'val'.
166 0000001E ;
167 0000001E ; Caller(s) : Application.
168 0000001E ;
169 0000001E ; This function is an INTERNAL CPU module
function but MAY be called by application
170 0000001E ; function(s).
171 0000001E ;
172 0000001E ; Note(s) : (1) (a) Supports 32-bit data value size
as configured by 'CPU_DATA' (see 'cpu.h
173 0000001E ; CPU WORD CONFIGURATION Note #1'
).
ARM Macro Assembler Page 5
174 0000001E ;
175 0000001E ; (b) For 32-bit values :
176 0000001E ;
177 0000001E ; b31 b30 b29 ... b04 b
03 b02 b01 b00 # Leading Zeros
178 0000001E ; --- --- --- --- -
-- --- --- --- ---------------
179 0000001E ; 1 x x x
x x x x 0
180 0000001E ; 0 1 x x
x x x x 1
181 0000001E ; 0 0 1 x
x x x x 2
182 0000001E ; : : : :
: : : : :
183 0000001E ; : : : :
: : : : :
184 0000001E ; 0 0 0 1
x x x x 27
185 0000001E ; 0 0 0 0
1 x x x 28
186 0000001E ; 0 0 0 0
0 1 x x 29
187 0000001E ; 0 0 0 0
0 0 1 x 30
188 0000001E ; 0 0 0 0
0 0 0 1 31
189 0000001E ; 0 0 0 0
0 0 0 0 32
190 0000001E ;
191 0000001E ;
192 0000001E ; (2) MUST be defined in 'cpu_a.asm' (or '
cpu_c.c') if CPU_CFG_LEAD_ZEROS_ASM_PRESENT is
193 0000001E ; #define'd in 'cpu_cfg.h' or 'cpu.h'.
194 0000001E ;*******************************************************
*************************************************
195 0000001E
196 0000001E CPU_CntLeadZeros
197 0000001E FAB0 F080 CLZ R0, R0 ; Count leading zer
os
198 00000022 4770 BX LR
199 00000024
200 00000024
201 00000024 ;$PAGE
202 00000024 ;*******************************************************
*************************************************
203 00000024 ; CPU_CntTrailZe
ros()
204 00000024 ; COUNT TRAILING
ZEROS
205 00000024 ;
206 00000024 ; Description : Counts the number of contiguous, least-s
ignificant, trailing zero bits before the
207 00000024 ; first binary one bit in a data value
.
208 00000024 ;
209 00000024 ; Prototype : CPU_DATA CPU_CntTrailZeros(CPU_DATA va
l);
ARM Macro Assembler Page 6
210 00000024 ;
211 00000024 ; Argument(s) : val Data value to count trailing
zero bits.
212 00000024 ;
213 00000024 ; Return(s) : Number of contiguous, least-significant,
trailing zero bits in 'val'.
214 00000024 ;
215 00000024 ; Caller(s) : Application.
216 00000024 ;
217 00000024 ; This function is an INTERNAL CPU module
function but MAY be called by application
218 00000024 ; function(s).
219 00000024 ;
220 00000024 ; Note(s) : (1) (a) Supports 32-bit data value size
as configured by 'CPU_DATA' (see 'cpu.h
221 00000024 ; CPU WORD CONFIGURATION Note #1'
).
222 00000024 ;
223 00000024 ; (b) For 32-bit values :
224 00000024 ;
225 00000024 ; b31 b30 b29 b28 b27 .
.. b02 b01 b00 # Trailing Zeros
226 00000024 ; --- --- --- --- ---
--- --- --- ----------------
227 00000024 ; x x x x x
x x 1 0
228 00000024 ; x x x x x
x 1 0 1
229 00000024 ; x x x x x
1 0 0 2
230 00000024 ; : : : : :
: : : :
231 00000024 ; : : : : :
: : : :
232 00000024 ; x x x x 1
0 0 0 27
233 00000024 ; x x x 1 0
0 0 0 28
234 00000024 ; x x 1 0 0
0 0 0 29
235 00000024 ; x 1 0 0 0
0 0 0 30
236 00000024 ; 1 0 0 0 0
0 0 0 31
237 00000024 ; 0 0 0 0 0
0 0 0 32
238 00000024 ;
239 00000024 ;
240 00000024 ; (2) MUST be defined in 'cpu_a.asm' (or '
cpu_c.c') if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT is
241 00000024 ; #define'd in 'cpu_cfg.h' or 'cpu.h'.
242 00000024 ;*******************************************************
*************************************************
243 00000024
244 00000024 CPU_CntTrailZeros
245 00000024 FA90 F0A0 RBIT R0, R0 ; Reverse bits
246 00000028 FAB0 F080 CLZ R0, R0 ; Count trailing ze
ros
ARM Macro Assembler Page 7
247 0000002C 4770 BX LR
248 0000002E
249 0000002E
250 0000002E ;$PAGE
251 0000002E ;*******************************************************
*************************************************
252 0000002E ; CPU_RevBits
()
253 0000002E ; REVERSE BIT
S
254 0000002E ;
255 0000002E ; Description : Reverses the bits in a data value.
256 0000002E ;
257 0000002E ; Prototypes : CPU_DATA CPU_RevBits(CPU_DATA val);
258 0000002E ;
259 0000002E ; Argument(s) : val Data value to reverse bits.
260 0000002E ;
261 0000002E ; Return(s) : Value with all bits in 'val' reversed (s
ee Note #1).
262 0000002E ;
263 0000002E ; Caller(s) : Application.
264 0000002E ;
265 0000002E ; This function is an INTERNAL CPU module
function but MAY be called by application function(s).
266 0000002E ;
267 0000002E ; Note(s) : (1) The final, reversed data value for '
val' is such that :
268 0000002E ;
269 0000002E ; 'val's final bit 0 = 'va
l's original bit N
270 0000002E ; 'val's final bit 1 = 'va
l's original bit (N - 1)
271 0000002E ; 'val's final bit 2 = 'va
l's original bit (N - 2)
272 0000002E ;
273 0000002E ; ...
...
274 0000002E ;
275 0000002E ; 'val's final bit (N - 2) = 'va
l's original bit 2
276 0000002E ; 'val's final bit (N - 1) = 'va
l's original bit 1
277 0000002E ; 'val's final bit N = 'va
l's original bit 0
278 0000002E ;*******************************************************
*************************************************
279 0000002E
280 0000002E CPU_RevBits
281 0000002E FA90 F0A0 RBIT R0, R0 ; Reverse bits
282 00000032 4770 BX LR
283 00000034
284 00000034
285 00000034 ;$PAGE
286 00000034 ;*******************************************************
*************************************************
287 00000034 ; CPU ASSEMBLY PORT
FILE END
288 00000034 ;*******************************************************
*************************************************
ARM Macro Assembler Page 8
289 00000034
290 00000034 END
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
ork --depend=.\flash\obj\cpu_a.d -o.\flash\obj\cpu_a.o -I.\RTE\_BMU_21S_APP -ID
:\Program\MDK\Pack\Keil\STM32F1xx_DFP\2.4.0\Device\Include -IC:\Keil_v5\ARM\CMS
IS\Include -ID:\Program\MDK\Pack\Keil\STM32F1xx_DFP\2.4.0 --predefine="__MICROL
IB SETA 1" --predefine="__UVISION_VERSION SETA 525" --predefine="STM32F10X_MD S
ETA 1" --list=.\flash\lst\cpu_a.lst ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cp
u_a.asm
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 59 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Uses
None
Comment: .text unused
CPU_CntLeadZeros 0000001E
Symbol: CPU_CntLeadZeros
Definitions
At line 196 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Uses
At line 50 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Comment: CPU_CntLeadZeros used once
CPU_CntTrailZeros 00000024
Symbol: CPU_CntTrailZeros
Definitions
At line 244 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Uses
At line 51 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Comment: CPU_CntTrailZeros used once
CPU_IntDis 00000000
Symbol: CPU_IntDis
Definitions
At line 75 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Uses
At line 40 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Comment: CPU_IntDis used once
CPU_IntEn 00000004
Symbol: CPU_IntEn
Definitions
At line 80 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Uses
At line 41 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Comment: CPU_IntEn used once
CPU_RevBits 0000002E
Symbol: CPU_RevBits
Definitions
At line 280 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Uses
At line 52 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Comment: CPU_RevBits used once
CPU_SR_Restore 00000010
Symbol: CPU_SR_Restore
Definitions
At line 117 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Uses
At line 44 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Comment: CPU_SR_Restore used once
CPU_SR_Save 00000008
Symbol: CPU_SR_Save
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
Definitions
At line 111 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Uses
At line 43 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Comment: CPU_SR_Save used once
CPU_WaitForExcept 0000001A
Symbol: CPU_WaitForExcept
Definitions
At line 148 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Uses
At line 47 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Comment: CPU_WaitForExcept used once
CPU_WaitForInt 00000016
Symbol: CPU_WaitForInt
Definitions
At line 133 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Uses
At line 46 in file ..\UCOSIII\uC-CPU\ARM-Cortex-M3\RealView\cpu_a.asm
Comment: CPU_WaitForInt used once
10 symbols
343 symbols in table

678
USER/FLASH/lst/lib_mem_a.lst Normal file
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@@ -0,0 +1,678 @@
ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
2 00000000 ; uC/LIB
3 00000000 ; CUSTOM LIBRARY
MODULES
4 00000000 ;
5 00000000 ; (c) Copyright 2004-2011; Micr
ium, Inc.; Weston, FL
6 00000000 ;
7 00000000 ; All rights reserved. Protected by inter
national copyright laws.
8 00000000 ;
9 00000000 ; uC/LIB is provided in source form to reg
istered licensees ONLY. It is
10 00000000 ; illegal to distribute this source code t
o any third party unless you receive
11 00000000 ; written permission by an authorized Micr
ium representative. Knowledge of
12 00000000 ; the source code may NOT be used to devel
op a similar product.
13 00000000 ;
14 00000000 ; Please help us continue to provide the E
mbedded community with the finest
15 00000000 ; software available. Your honesty is gre
atly appreciated.
16 00000000 ;
17 00000000 ; You can contact us at www.micrium.com.
18 00000000 ;*******************************************************
*************************************************
19 00000000
20 00000000
21 00000000 ;*******************************************************
*************************************************
22 00000000 ;
23 00000000 ; STANDARD MEMORY OP
ERATIONS
24 00000000 ;
25 00000000 ; ARM-Cortex-M
3
26 00000000 ; RealView Developme
nt Suite
27 00000000 ; RealView Microcontroller De
velopment Kit (MDK)
28 00000000 ; ARM Developer Sui
te (ADS)
29 00000000 ; Keil uVision
30 00000000 ;
31 00000000 ; Filename : lib_mem_a.asm
32 00000000 ; Version : V1.36.01.00
33 00000000 ; Programmer(s) : JDH
34 00000000 ; BAN
35 00000000 ;*******************************************************
*************************************************
36 00000000 ; Note(s) : (1) NO compiler-supplied standard libr
ary functions are used in library or product software.
37 00000000 ;
38 00000000 ; (a) ALL standard library functions
are implemented in the custom library modules :
ARM Macro Assembler Page 2
39 00000000 ;
40 00000000 ; (1) \<Custom Library Directory
>\lib*.*
41 00000000 ;
42 00000000 ; (2) \<Custom Library Directory
>\Ports\<cpu>\<compiler>\lib*_a.*
43 00000000 ;
44 00000000 ; where
45 00000000 ; <Custom Library
Directory> directory path for custom library softwa
re
46 00000000 ; <cpu>
directory name for specific processor (C
PU)
47 00000000 ; <compiler>
directory name for specific compiler
48 00000000 ;
49 00000000 ; (b) Product-specific library funct
ions are implemented in individual products.
50 00000000 ;
51 00000000 ; (2) Assumes ARM CPU mode configured fo
r Little Endian.
52 00000000 ;*******************************************************
*************************************************
53 00000000
54 00000000
55 00000000 ;*******************************************************
*************************************************
56 00000000 ; PUBLIC FUNCT
IONS
57 00000000 ;*******************************************************
*************************************************
58 00000000
59 00000000 EXPORT Mem_Copy
60 00000000
61 00000000
62 00000000 ;*******************************************************
*************************************************
63 00000000 ; CODE GENERATION D
IRECTIVES
64 00000000 ;*******************************************************
*************************************************
65 00000000
66 00000000 AREA |.text|, CODE, READONLY, ALIGN=
2
67 00000000 THUMB
68 00000000 REQUIRE8
69 00000000 PRESERVE8
70 00000000
71 00000000
72 00000000 ;$PAGE
73 00000000 ;*******************************************************
*************************************************
74 00000000 ; Mem_Copy()
75 00000000 ;
76 00000000 ; Description : Copy data octets from one buffer to anot
her buffer.
77 00000000 ;
ARM Macro Assembler Page 3
78 00000000 ; Argument(s) : pdest Pointer to destination memor
y buffer.
79 00000000 ;
80 00000000 ; psrc Pointer to source memor
y buffer.
81 00000000 ;
82 00000000 ; size Number of data buffer octets
to copy.
83 00000000 ;
84 00000000 ; Return(s) : none.
85 00000000 ;
86 00000000 ; Caller(s) : Application.
87 00000000 ;
88 00000000 ; Note(s) : (1) Null copies allowed (i.e. 0-octet si
ze).
89 00000000 ;
90 00000000 ; (2) Memory buffers NOT checked for overl
apping.
91 00000000 ;
92 00000000 ; (3) Modulo arithmetic is used to determi
ne whether a memory buffer starts on a 'CPU_ALIGN'
93 00000000 ; address boundary.
94 00000000 ;
95 00000000 ; (4) ARM Cortex-M3 processors use a subse
t of the ARM Thumb-2 instruction set which does
96 00000000 ; NOT support 16-bit conditional branc
h instructions but ONLY supports 8-bit conditional
97 00000000 ; branch instructions.
98 00000000 ;
99 00000000 ; Therefore, branches exceeding 8-bit,
signed, relative offsets :
100 00000000 ;
101 00000000 ; (a) CANNOT be implemented with c
onditional branches; but ...
102 00000000 ; (b) MUST be implemented with non-c
onditional branches.
103 00000000 ;*******************************************************
*************************************************
104 00000000
105 00000000 ; void Mem_Copy (void *pdest, ; ==> R0
106 00000000 ; void *psrc, ; ==> R1
107 00000000 ; CPU_SIZE_T size) ; ==> R2
108 00000000
109 00000000 Mem_Copy
110 00000000 2800 CMP R0, #0
111 00000002 D100 BNE Mem_Copy_1
112 00000004 4770 BX LR ; return if pdest =
= NULL
113 00000006
114 00000006 Mem_Copy_1
115 00000006 2900 CMP R1, #0
116 00000008 D100 BNE Mem_Copy_2
117 0000000A 4770 BX LR ; return if psrc =
= NULL
118 0000000C
119 0000000C Mem_Copy_2
120 0000000C 2A00 CMP R2, #0
121 0000000E D100 BNE Mem_Copy_3
122 00000010 4770 BX LR ; return if size =
ARM Macro Assembler Page 4
= 0
123 00000012
124 00000012 Mem_Copy_3
125 00000012 E92D 1FF8 STMFD SP!, {R3-R12} ; save registers
on stack
126 00000016
127 00000016
128 00000016 ;$PAGE
129 00000016 Chk_Align_32 ; check if both des
t & src 32-bit alig
ned
130 00000016 F000 0303 AND R3, R0, #0x03
131 0000001A F001 0403 AND R4, R1, #0x03
132 0000001E 42A3 CMP R3, R4
133 00000020 D111 BNE Chk_Align_16 ; not 32-bit align
ed, check for 16-bi
t alignment
134 00000022
135 00000022 F1C3 0304 RSB R3, R3, #0x04 ; compute 1-2-3 p
re-copy bytes (to a
lign to the next 32
-bit boundary)
136 00000026 F003 0303 AND R3, R3, #0x03
137 0000002A
138 0000002A Pre_Copy_1
139 0000002A 2B01 CMP R3, #1 ; copy 1-2-3 bytes
(to align to the ne
xt 32-bit boundary)
140 0000002C D31D BCC Copy_32_1 ; start real 32-bit
copy
141 0000002E 2A01 CMP R2, #1 ; check if any more
data to copy
142 00000030 D200 BCS Pre_Copy_1_Cont
143 00000032 E0F2 B Mem_Copy_END ; no mor
e data to copy (see
Note #4b)
144 00000034
145 00000034 Pre_Copy_1_Cont
146 00000034 F811 4B01 LDRB R4, [R1], #1
147 00000038 F800 4B01 STRB R4, [R0], #1
148 0000003C F1A3 0301 SUB R3, R3, #1
149 00000040 F1A2 0201 SUB R2, R2, #1
150 00000044 E7F1 B Pre_Copy_1
151 00000046
152 00000046
153 00000046 Chk_Align_16 ; check if both des
t & src 16-bit alig
ned
154 00000046 F000 0301 AND R3, R0, #0x01
155 0000004A F001 0401 AND R4, R1, #0x01
156 0000004E 42A3 CMP R3, R4
157 00000050 D000 BEQ Pre_Copy_2
158 00000052 E094 B Copy_08_1 ; not 16-bit aligne
d, start 8-bit copy
(see Note #4b)
159 00000054
160 00000054 Pre_Copy_2
161 00000054 2B01 CMP R3, #1 ; copy 1 byte (to a
ARM Macro Assembler Page 5
lign to the next 16
-bit boundary)
162 00000056 D344 BCC Copy_16_1 ; start real 16-bit
copy
163 00000058
164 00000058 F811 4B01 LDRB R4, [R1], #1
165 0000005C F800 4B01 STRB R4, [R0], #1
166 00000060 F1A3 0301 SUB R3, R3, #1
167 00000064 F1A2 0201 SUB R2, R2, #1
168 00000068 E7F4 B Pre_Copy_2
169 0000006A
170 0000006A
171 0000006A Copy_32_1
172 0000006A F5B2 7FB4 CMP R2, #(04*10*09) ; Copy 9 chunks
of 10 32-bit words
(360 octets per lo
op)
173 0000006E D326 BCC Copy_32_2
174 00000070 E8B1 1FF8 LDMIA R1!, {R3-R12}
175 00000074 E8A0 1FF8 STMIA R0!, {R3-R12}
176 00000078 E8B1 1FF8 LDMIA R1!, {R3-R12}
177 0000007C E8A0 1FF8 STMIA R0!, {R3-R12}
178 00000080 E8B1 1FF8 LDMIA R1!, {R3-R12}
179 00000084 E8A0 1FF8 STMIA R0!, {R3-R12}
180 00000088 E8B1 1FF8 LDMIA R1!, {R3-R12}
181 0000008C E8A0 1FF8 STMIA R0!, {R3-R12}
182 00000090 E8B1 1FF8 LDMIA R1!, {R3-R12}
183 00000094 E8A0 1FF8 STMIA R0!, {R3-R12}
184 00000098 E8B1 1FF8 LDMIA R1!, {R3-R12}
185 0000009C E8A0 1FF8 STMIA R0!, {R3-R12}
186 000000A0 E8B1 1FF8 LDMIA R1!, {R3-R12}
187 000000A4 E8A0 1FF8 STMIA R0!, {R3-R12}
188 000000A8 E8B1 1FF8 LDMIA R1!, {R3-R12}
189 000000AC E8A0 1FF8 STMIA R0!, {R3-R12}
190 000000B0 E8B1 1FF8 LDMIA R1!, {R3-R12}
191 000000B4 E8A0 1FF8 STMIA R0!, {R3-R12}
192 000000B8 F5A2 72B4 SUB R2, R2, #(04*10*09)
193 000000BC E7D5 B Copy_32_1
194 000000BE
195 000000BE Copy_32_2
196 000000BE 2A28 CMP R2, #(04*10*01) ; Copy chunks o
f 10 32-bit words (
40 octets per loop)
197 000000C0 D306 BCC Copy_32_3
198 000000C2 E8B1 1FF8 LDMIA R1!, {R3-R12}
199 000000C6 E8A0 1FF8 STMIA R0!, {R3-R12}
200 000000CA F1A2 0228 SUB R2, R2, #(04*10*01)
201 000000CE E7F6 B Copy_32_2
202 000000D0
203 000000D0 Copy_32_3
204 000000D0 2A04 CMP R2, #(04*01*01) ; Copy remainin
g 32-bit words
205 000000D2 D306 BCC Copy_16_1
206 000000D4 F851 3B04 LDR R3, [R1], #4
207 000000D8 F840 3B04 STR R3, [R0], #4
208 000000DC F1A2 0204 SUB R2, R2, #(04*01*01)
209 000000E0 E7F6 B Copy_32_3
210 000000E2
ARM Macro Assembler Page 6
211 000000E2 ;$PAGE
212 000000E2 Copy_16_1
213 000000E2 2A20 CMP R2, #(02*01*16) ; Copy chunks o
f 16 16-bit words (
32 bytes per loop)
214 000000E4 D342 BCC Copy_16_2
215 000000E6 F831 3B02 LDRH R3, [R1], #2
216 000000EA F820 3B02 STRH R3, [R0], #2
217 000000EE F831 3B02 LDRH R3, [R1], #2
218 000000F2 F820 3B02 STRH R3, [R0], #2
219 000000F6 F831 3B02 LDRH R3, [R1], #2
220 000000FA F820 3B02 STRH R3, [R0], #2
221 000000FE F831 3B02 LDRH R3, [R1], #2
222 00000102 F820 3B02 STRH R3, [R0], #2
223 00000106 F831 3B02 LDRH R3, [R1], #2
224 0000010A F820 3B02 STRH R3, [R0], #2
225 0000010E F831 3B02 LDRH R3, [R1], #2
226 00000112 F820 3B02 STRH R3, [R0], #2
227 00000116 F831 3B02 LDRH R3, [R1], #2
228 0000011A F820 3B02 STRH R3, [R0], #2
229 0000011E F831 3B02 LDRH R3, [R1], #2
230 00000122 F820 3B02 STRH R3, [R0], #2
231 00000126 F831 3B02 LDRH R3, [R1], #2
232 0000012A F820 3B02 STRH R3, [R0], #2
233 0000012E F831 3B02 LDRH R3, [R1], #2
234 00000132 F820 3B02 STRH R3, [R0], #2
235 00000136 F831 3B02 LDRH R3, [R1], #2
236 0000013A F820 3B02 STRH R3, [R0], #2
237 0000013E F831 3B02 LDRH R3, [R1], #2
238 00000142 F820 3B02 STRH R3, [R0], #2
239 00000146 F831 3B02 LDRH R3, [R1], #2
240 0000014A F820 3B02 STRH R3, [R0], #2
241 0000014E F831 3B02 LDRH R3, [R1], #2
242 00000152 F820 3B02 STRH R3, [R0], #2
243 00000156 F831 3B02 LDRH R3, [R1], #2
244 0000015A F820 3B02 STRH R3, [R0], #2
245 0000015E F831 3B02 LDRH R3, [R1], #2
246 00000162 F820 3B02 STRH R3, [R0], #2
247 00000166 F1A2 0220 SUB R2, R2, #(02*01*16)
248 0000016A E7BA B Copy_16_1
249 0000016C
250 0000016C Copy_16_2
251 0000016C 2A02 CMP R2, #(02*01*01) ; Copy remainin
g 16-bit words
252 0000016E D306 BCC Copy_08_1
253 00000170 F831 3B02 LDRH R3, [R1], #2
254 00000174 F820 3B02 STRH R3, [R0], #2
255 00000178 F1A2 0202 SUB R2, R2, #(02*01*01)
256 0000017C E7F6 B Copy_16_2
257 0000017E
258 0000017E ;$PAGE
259 0000017E Copy_08_1
260 0000017E 2A10 CMP R2, #(01*01*16) ; Copy chunks o
f 16 8-bit words (1
6 bytes per loop)
261 00000180 D342 BCC Copy_08_2
262 00000182 F811 3B01 LDRB R3, [R1], #1
263 00000186 F800 3B01 STRB R3, [R0], #1
264 0000018A F811 3B01 LDRB R3, [R1], #1
ARM Macro Assembler Page 7
265 0000018E F800 3B01 STRB R3, [R0], #1
266 00000192 F811 3B01 LDRB R3, [R1], #1
267 00000196 F800 3B01 STRB R3, [R0], #1
268 0000019A F811 3B01 LDRB R3, [R1], #1
269 0000019E F800 3B01 STRB R3, [R0], #1
270 000001A2 F811 3B01 LDRB R3, [R1], #1
271 000001A6 F800 3B01 STRB R3, [R0], #1
272 000001AA F811 3B01 LDRB R3, [R1], #1
273 000001AE F800 3B01 STRB R3, [R0], #1
274 000001B2 F811 3B01 LDRB R3, [R1], #1
275 000001B6 F800 3B01 STRB R3, [R0], #1
276 000001BA F811 3B01 LDRB R3, [R1], #1
277 000001BE F800 3B01 STRB R3, [R0], #1
278 000001C2 F811 3B01 LDRB R3, [R1], #1
279 000001C6 F800 3B01 STRB R3, [R0], #1
280 000001CA F811 3B01 LDRB R3, [R1], #1
281 000001CE F800 3B01 STRB R3, [R0], #1
282 000001D2 F811 3B01 LDRB R3, [R1], #1
283 000001D6 F800 3B01 STRB R3, [R0], #1
284 000001DA F811 3B01 LDRB R3, [R1], #1
285 000001DE F800 3B01 STRB R3, [R0], #1
286 000001E2 F811 3B01 LDRB R3, [R1], #1
287 000001E6 F800 3B01 STRB R3, [R0], #1
288 000001EA F811 3B01 LDRB R3, [R1], #1
289 000001EE F800 3B01 STRB R3, [R0], #1
290 000001F2 F811 3B01 LDRB R3, [R1], #1
291 000001F6 F800 3B01 STRB R3, [R0], #1
292 000001FA F811 3B01 LDRB R3, [R1], #1
293 000001FE F800 3B01 STRB R3, [R0], #1
294 00000202 F1A2 0210 SUB R2, R2, #(01*01*16)
295 00000206 E7BA B Copy_08_1
296 00000208
297 00000208 Copy_08_2
298 00000208 2A01 CMP R2, #(01*01*01) ; Copy remainin
g 8-bit words
299 0000020A D306 BCC Mem_Copy_END
300 0000020C F811 3B01 LDRB R3, [R1], #1
301 00000210 F800 3B01 STRB R3, [R0], #1
302 00000214 F1A2 0201 SUB R2, R2, #(01*01*01)
303 00000218 E7F6 B Copy_08_2
304 0000021A
305 0000021A
306 0000021A Mem_Copy_END
307 0000021A E8BD 1FF8 LDMFD SP!, {R3-R12} ; restore registe
rs from stack
308 0000021E 4770 BX LR ; return
309 00000220
310 00000220
311 00000220 END
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
ork --depend=.\flash\obj\lib_mem_a.d -o.\flash\obj\lib_mem_a.o -I.\RTE\_BMU_21S
_APP -ID:\Program\MDK\Pack\Keil\STM32F1xx_DFP\2.4.0\Device\Include -IC:\Keil_v5
\ARM\CMSIS\Include -ID:\Program\MDK\Pack\Keil\STM32F1xx_DFP\2.4.0 --predefine="
__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 525" --predefine="STM32F
10X_MD SETA 1" --list=.\flash\lst\lib_mem_a.lst ..\UCOSIII\uC-LIB\Ports\ARM-Cor
tex-M3\RealView\lib_mem_a.asm
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 66 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_mem
_a.asm
Uses
None
Comment: .text unused
Chk_Align_16 00000046
Symbol: Chk_Align_16
Definitions
At line 153 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 133 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Comment: Chk_Align_16 used once
Chk_Align_32 00000016
Symbol: Chk_Align_32
Definitions
At line 129 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
None
Comment: Chk_Align_32 unused
Copy_08_1 0000017E
Symbol: Copy_08_1
Definitions
At line 259 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 158 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 252 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 295 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Copy_08_2 00000208
Symbol: Copy_08_2
Definitions
At line 297 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 261 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 303 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Copy_16_1 000000E2
Symbol: Copy_16_1
Definitions
At line 212 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
m_a.asm
Uses
At line 162 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 205 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 248 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Copy_16_2 0000016C
Symbol: Copy_16_2
Definitions
At line 250 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 214 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 256 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Copy_32_1 0000006A
Symbol: Copy_32_1
Definitions
At line 171 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 140 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 193 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Copy_32_2 000000BE
Symbol: Copy_32_2
Definitions
At line 195 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 173 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 201 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Copy_32_3 000000D0
Symbol: Copy_32_3
Definitions
At line 203 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 197 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 209 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Mem_Copy 00000000
ARM Macro Assembler Page 3 Alphabetic symbol ordering
Relocatable symbols
Symbol: Mem_Copy
Definitions
At line 109 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 59 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_mem
_a.asm
Comment: Mem_Copy used once
Mem_Copy_1 00000006
Symbol: Mem_Copy_1
Definitions
At line 114 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 111 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Comment: Mem_Copy_1 used once
Mem_Copy_2 0000000C
Symbol: Mem_Copy_2
Definitions
At line 119 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 116 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Comment: Mem_Copy_2 used once
Mem_Copy_3 00000012
Symbol: Mem_Copy_3
Definitions
At line 124 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 121 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Comment: Mem_Copy_3 used once
Mem_Copy_END 0000021A
Symbol: Mem_Copy_END
Definitions
At line 306 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 143 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 299 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Pre_Copy_1 0000002A
Symbol: Pre_Copy_1
Definitions
At line 138 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 150 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
ARM Macro Assembler Page 4 Alphabetic symbol ordering
Relocatable symbols
Comment: Pre_Copy_1 used once
Pre_Copy_1_Cont 00000034
Symbol: Pre_Copy_1_Cont
Definitions
At line 145 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 142 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Comment: Pre_Copy_1_Cont used once
Pre_Copy_2 00000054
Symbol: Pre_Copy_2
Definitions
At line 160 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
Uses
At line 157 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
At line 168 in file ..\UCOSIII\uC-LIB\Ports\ARM-Cortex-M3\RealView\lib_me
m_a.asm
18 symbols
351 symbols in table

521
USER/FLASH/lst/os_cpu_a.lst Normal file
View File

@@ -0,0 +1,521 @@
ARM Macro Assembler Page 1
1 00000000 ;
2 00000000 ;*******************************************************
*************************************************
3 00000000 ; uC/OS-I
II
4 00000000 ; The Real-Time
Kernel
5 00000000 ;
6 00000000 ;
7 00000000 ; (c) Copyright 2009-2010; Mic
rium, Inc.; Weston, FL
8 00000000 ; All rights reserved. Protected by
international copyright laws.
9 00000000 ;
10 00000000 ; ARM Cortex-M
3 Port
11 00000000 ;
12 00000000 ; File : OS_CPU_A.ASM
13 00000000 ; Version : V3.01.2
14 00000000 ; By : JJL
15 00000000 ; BAN
16 00000000 ;
17 00000000 ; For : ARMv7M Cortex-M3
18 00000000 ; Mode : Thumb2
19 00000000 ; Toolchain : RealView Development Suite
20 00000000 ; RealView Microcontroller Development Kit (
MDK)
21 00000000 ; ARM Developer Suite (ADS)
22 00000000 ; Keil uVision
23 00000000 ;*******************************************************
*************************************************
24 00000000 ;
25 00000000
26 00000000 ;*******************************************************
*************************************************
27 00000000 ; PUBLIC FUNCTI
ONS
28 00000000 ;*******************************************************
*************************************************
29 00000000
30 00000000 IMPORT OSRunning ; External referenc
es
31 00000000 IMPORT OSPrioCur
32 00000000 IMPORT OSPrioHighRdy
33 00000000 IMPORT OSTCBCurPtr
34 00000000 IMPORT OSTCBHighRdyPtr
35 00000000 IMPORT OSIntExit
36 00000000 IMPORT OSTaskSwHook
37 00000000 IMPORT OS_CPU_ExceptStkBase
38 00000000
39 00000000
40 00000000 EXPORT OSStartHighRdy ; Functions decl
ared in this file
41 00000000 EXPORT OS_CPU_PendSVHandler
42 00000000
43 00000000 ;PAGE
44 00000000 ;*******************************************************
*************************************************
45 00000000 ; EQUATES
ARM Macro Assembler Page 2
46 00000000 ;*******************************************************
*************************************************
47 00000000
48 00000000 E000ED04
NVIC_INT_CTRL
EQU 0xE000ED04 ; Interrupt control
state register.
49 00000000 E000ED22
NVIC_SYSPRI14
EQU 0xE000ED22 ; System priority r
egister (priority 1
4).
50 00000000 000000FF
NVIC_PENDSV_PRI
EQU 0xFF ; PendSV priority v
alue (lowest).
51 00000000 10000000
NVIC_PENDSVSET
EQU 0x10000000 ; Value to trigger
PendSV exception.
52 00000000
53 00000000
54 00000000 ;*******************************************************
*************************************************
55 00000000 ; CODE GENERATION DI
RECTIVES
56 00000000 ;*******************************************************
*************************************************
57 00000000
58 00000000 PRESERVE8
59 00000000 THUMB
60 00000000
61 00000000 AREA CODE, CODE, READONLY
62 00000000
63 00000000
64 00000000 ;PAGE
65 00000000 ;*******************************************************
*************************************************
66 00000000 ; START MULTITAS
KING
67 00000000 ; void OSStartHighR
dy(void)
68 00000000 ;
69 00000000 ; Note(s) : 1) This function triggers a PendSV exception
(essentially, causes a context switch) to cause
70 00000000 ; the first task to start.
71 00000000 ;
72 00000000 ; 2) OSStartHighRdy() MUST:
73 00000000 ; a) Setup PendSV exception priority to low
est;
74 00000000 ; b) Set initial PSP to 0, to tell context
switcher this is first run;
75 00000000 ; c) Set the main stack to OS_CPU_ExceptStk
Base
76 00000000 ; d) Trigger PendSV exception;
77 00000000 ; e) Enable interrupts (tasks will run with
interrupts enabled).
78 00000000 ;*******************************************************
*************************************************
ARM Macro Assembler Page 3
79 00000000
80 00000000 OSStartHighRdy
81 00000000 4818 LDR R0, =NVIC_SYSPRI14 ; Set the Pe
ndSV exception prio
rity
82 00000002 F04F 01FF LDR R1, =NVIC_PENDSV_PRI
83 00000006 7001 STRB R1, [R0]
84 00000008
85 00000008 2000 MOVS R0, #0 ; Set the PSP to 0
for initial context
switch call
86 0000000A F380 8809 MSR PSP, R0
87 0000000E
88 0000000E 4816 LDR R0, =OS_CPU_ExceptStkBase ; Ini
tialize the MSP to
the OS_CPU_ExceptSt
kBase
89 00000010 6801 LDR R1, [R0]
90 00000012 F381 8808 MSR MSP, R1
91 00000016
92 00000016 4815 LDR R0, =NVIC_INT_CTRL ; Trigger th
e PendSV exception
(causes context swi
tch)
93 00000018 F04F 5180 LDR R1, =NVIC_PENDSVSET
94 0000001C 6001 STR R1, [R0]
95 0000001E
96 0000001E B662 CPSIE I ; Enable interrupts
at processor level
97 00000020
98 00000020 OSStartHang
99 00000020 E7FE B OSStartHang ; Should never get
here
100 00000022
101 00000022
102 00000022 ;PAGE
103 00000022 ;*******************************************************
*************************************************
104 00000022 ; HANDLE PendSV EX
CEPTION
105 00000022 ; void OS_CPU_PendSVHa
ndler(void)
106 00000022 ;
107 00000022 ; Note(s) : 1) PendSV is used to cause a context switch.
This is a recommended method for performing
108 00000022 ; context switches with Cortex-M3. This is
because the Cortex-M3 auto-saves half of the
109 00000022 ; processor context on any exception, and r
estores same on return from exception. So only
110 00000022 ; saving of R4-R11 is required and fixing u
p the stack pointers. Using the PendSV exception
111 00000022 ; this way means that context saving and re
storing is identical whether it is initiated from
112 00000022 ; a thread or occurs due to an interrupt or
exception.
113 00000022 ;
114 00000022 ; 2) Pseudo-code is:
115 00000022 ; a) Get the process SP, if 0 then skip (go
ARM Macro Assembler Page 4
to d) the saving part (first context switch);
116 00000022 ; b) Save remaining regs r4-r11 on process
stack;
117 00000022 ; c) Save the process SP in its TCB, OSTCBC
urPtr->OSTCBStkPtr = SP;
118 00000022 ; d) Call OSTaskSwHook();
119 00000022 ; e) Get current high priority, OSPrioCur =
OSPrioHighRdy;
120 00000022 ; f) Get current ready thread TCB, OSTCBCur
Ptr = OSTCBHighRdyPtr;
121 00000022 ; g) Get new process SP from TCB, SP = OSTC
BHighRdyPtr->OSTCBStkPtr;
122 00000022 ; h) Restore R4-R11 from new process stack;
123 00000022 ; i) Perform exception return which will re
store remaining context.
124 00000022 ;
125 00000022 ; 3) On entry into PendSV handler:
126 00000022 ; a) The following have been saved on the p
rocess stack (by processor):
127 00000022 ; xPSR, PC, LR, R12, R0-R3
128 00000022 ; b) Processor mode is switched to Handler
mode (from Thread mode)
129 00000022 ; c) Stack is Main stack (switched from Pro
cess stack)
130 00000022 ; d) OSTCBCurPtr points to the OS_TCB
of the task to suspend
131 00000022 ; OSTCBHighRdyPtr points to the OS_TCB
of the task to resume
132 00000022 ;
133 00000022 ; 4) Since PendSV is set to lowest priority in
the system (by OSStartHighRdy() above), we
134 00000022 ; know that it will only be run when no oth
er exception or interrupt is active, and
135 00000022 ; therefore safe to assume that context bei
ng switched out was using the process stack (PSP).
136 00000022 ;*******************************************************
*************************************************
137 00000022
138 00000022 OS_CPU_PendSVHandler
139 00000022 B672 CPSID I ; Prevent interrupt
ion during context
switch
140 00000024 F3EF 8009 MRS R0, PSP ; PSP is process st
ack pointer
141 00000028 B128 CBZ R0, OS_CPU_PendSVHandler_nosave
; Skip register sav
e the first time
142 0000002A
143 0000002A 3820 SUBS R0, R0, #0x20 ; Save remaining
regs r4-11 on proce
ss stack
144 0000002C E880 0FF0 STM R0, {R4-R11}
145 00000030
146 00000030 490F LDR R1, =OSTCBCurPtr ; OSTCBCurPtr-
>OSTCBStkPtr = SP;
147 00000032 6809 LDR R1, [R1]
148 00000034 6008 STR R0, [R1] ; R0 is SP of proce
ARM Macro Assembler Page 5
ss being switched o
ut
149 00000036
150 00000036 ; At this point, entire context of process has been save
d
151 00000036 OS_CPU_PendSVHandler_nosave
152 00000036 B500 PUSH {R14} ; Save LR exc_retur
n value
153 00000038 480E LDR R0, =OSTaskSwHook
; OSTaskSwHook();
154 0000003A 4780 BLX R0
155 0000003C F85D EB04 POP {R14}
156 00000040
157 00000040 480D LDR R0, =OSPrioCur ; OSPrioCur =
OSPrioHighRdy;
158 00000042 490E LDR R1, =OSPrioHighRdy
159 00000044 780A LDRB R2, [R1]
160 00000046 7002 STRB R2, [R0]
161 00000048
162 00000048 4809 LDR R0, =OSTCBCurPtr ; OSTCBCurPtr
= OSTCBHighRdyPtr;
163 0000004A 490D LDR R1, =OSTCBHighRdyPtr
164 0000004C 680A LDR R2, [R1]
165 0000004E 6002 STR R2, [R0]
166 00000050
167 00000050 6810 LDR R0, [R2] ; R0 is new process
SP; SP = OSTCBHigh
RdyPtr->StkPtr;
168 00000052 E890 0FF0 LDM R0, {R4-R11} ; Restore r4-11 fr
om new process stac
k
169 00000056 3020 ADDS R0, R0, #0x20
170 00000058 F380 8809 MSR PSP, R0 ; Load PSP with new
process SP
171 0000005C F04E 0E04 ORR LR, LR, #0x04 ; Ensure exceptio
n return uses proce
ss stack
172 00000060 B662 CPSIE I
173 00000062 4770 BX LR ; Exception return
will restore remain
ing context
174 00000064
175 00000064 END
E000ED22
00000000
E000ED04
00000000
00000000
00000000
00000000
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
ork --depend=.\flash\obj\os_cpu_a.d -o.\flash\obj\os_cpu_a.o -I.\RTE\_BMU_21S_A
PP -ID:\Program\MDK\Pack\Keil\STM32F1xx_DFP\2.4.0\Device\Include -IC:\Keil_v5\A
RM\CMSIS\Include -ID:\Program\MDK\Pack\Keil\STM32F1xx_DFP\2.4.0 --predefine="__
MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 525" --predefine="STM32F10
X_MD SETA 1" --list=.\flash\lst\os_cpu_a.lst ..\UCOSIII\uCOS-III\Ports\ARM-Cort
ex-M3\Generic\RealView\os_cpu_a.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
CODE 00000000
Symbol: CODE
Definitions
At line 61 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
None
Comment: CODE unused
OSStartHang 00000020
Symbol: OSStartHang
Definitions
At line 98 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 99 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Comment: OSStartHang used once
OSStartHighRdy 00000000
Symbol: OSStartHighRdy
Definitions
At line 80 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 40 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Comment: OSStartHighRdy used once
OS_CPU_PendSVHandler 00000022
Symbol: OS_CPU_PendSVHandler
Definitions
At line 138 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealV
iew\os_cpu_a.s
Uses
At line 41 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Comment: OS_CPU_PendSVHandler used once
OS_CPU_PendSVHandler_nosave 00000036
Symbol: OS_CPU_PendSVHandler_nosave
Definitions
At line 151 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealV
iew\os_cpu_a.s
Uses
At line 141 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealV
iew\os_cpu_a.s
Comment: OS_CPU_PendSVHandler_nosave used once
5 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
NVIC_INT_CTRL E000ED04
Symbol: NVIC_INT_CTRL
Definitions
At line 48 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 92 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Comment: NVIC_INT_CTRL used once
NVIC_PENDSVSET 10000000
Symbol: NVIC_PENDSVSET
Definitions
At line 51 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 93 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Comment: NVIC_PENDSVSET used once
NVIC_PENDSV_PRI 000000FF
Symbol: NVIC_PENDSV_PRI
Definitions
At line 50 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 82 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Comment: NVIC_PENDSV_PRI used once
NVIC_SYSPRI14 E000ED22
Symbol: NVIC_SYSPRI14
Definitions
At line 49 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 81 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Comment: NVIC_SYSPRI14 used once
4 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
OSIntExit 00000000
Symbol: OSIntExit
Definitions
At line 35 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
None
Comment: OSIntExit unused
OSPrioCur 00000000
Symbol: OSPrioCur
Definitions
At line 31 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 157 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealV
iew\os_cpu_a.s
Comment: OSPrioCur used once
OSPrioHighRdy 00000000
Symbol: OSPrioHighRdy
Definitions
At line 32 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 158 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealV
iew\os_cpu_a.s
Comment: OSPrioHighRdy used once
OSRunning 00000000
Symbol: OSRunning
Definitions
At line 30 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
None
Comment: OSRunning unused
OSTCBCurPtr 00000000
Symbol: OSTCBCurPtr
Definitions
At line 33 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 146 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealV
iew\os_cpu_a.s
At line 162 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealV
iew\os_cpu_a.s
OSTCBHighRdyPtr 00000000
Symbol: OSTCBHighRdyPtr
Definitions
At line 34 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 163 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealV
iew\os_cpu_a.s
ARM Macro Assembler Page 2 Alphabetic symbol ordering
External symbols
Comment: OSTCBHighRdyPtr used once
OSTaskSwHook 00000000
Symbol: OSTaskSwHook
Definitions
At line 36 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 153 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealV
iew\os_cpu_a.s
Comment: OSTaskSwHook used once
OS_CPU_ExceptStkBase 00000000
Symbol: OS_CPU_ExceptStkBase
Definitions
At line 37 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Uses
At line 88 in file ..\UCOSIII\uCOS-III\Ports\ARM-Cortex-M3\Generic\RealVi
ew\os_cpu_a.s
Comment: OS_CPU_ExceptStkBase used once
8 symbols
352 symbols in table

1179
USER/FLASH/lst/startup_stm32f10x_md.lst Normal file
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