Backup before error handling refactoring
This commit is contained in:
jkwoo
41
USER/DebugConfig/BMCB_APP_STM32F407VGTx.dbgconf
Normal file
41
USER/DebugConfig/BMCB_APP_STM32F407VGTx.dbgconf
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@@ -0,0 +1,41 @@
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||||
// <<< Use Configuration Wizard in Context Menu >>>
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||||
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||||
// <h>Debug MCU Configuration
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||||
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
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||||
// <o.1> DBG_STOP <i> Debug Stop Mode
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||||
// <o.2> DBG_STANDBY <i> Debug Standby Mode
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// </h>
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DbgMCU_CR = 0x00000007;
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||||
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||||
// <h> Debug MCU APB1 Freeze
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// <o.0> DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
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// <o.1> DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
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||||
// <o.2> DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
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// <o.3> DBG_TIM5_STOP <i> Timer 5 Stopped when Core is halted
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// <o.4> DBG_TIM6_STOP <i> Timer 6 Stopped when Core is halted
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// <o.5> DBG_TIM7_STOP <i> Timer 7 Stopped when Core is halted
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// <o.6> DBG_TIM12_STOP <i> Timer 12 Stopped when Core is halted
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// <o.7> DBG_TIM13_STOP <i> Timer 13 Stopped when Core is halted
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// <o.8> DBG_TIM14_STOP <i> Timer 14 Stopped when Core is halted
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// <o.10> DBG_RTC_STOP <i> RTC Stopped when Core is halted
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// <o.11> DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
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// <o.12> DBG_IWDG_STOP <i> Independent Watchdog Stopped when Core is halted
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// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS Timeout Mode Stopped when Core is halted
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// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS Timeout Mode Stopped when Core is halted
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// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS Timeout Mode Stopped when Core is halted
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// <o.25> DBG_CAN1_STOP <i> CAN1 Stopped when Core is halted
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// <o.26> DBG_CAN2_STOP <i> CAN2 Stopped when Core is halted
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// </h>
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DbgMCU_APB1_Fz = 0x00000000;
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// <h> Debug MCU APB2 Freeze
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// <o.0> DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
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// <o.1> DBG_TIM8_STOP <i> Timer 8 Stopped when Core is halted
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// <o.16> DBG_TIM9_STOP <i> Timer 9 Stopped when Core is halted
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// <o.17> DBG_TIM10_STOP <i> Timer 10 Stopped when Core is halted
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// <o.18> DBG_TIM11_STOP <i> Timer 11 Stopped when Core is halted
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <<< end of configuration section >>>
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36
USER/DebugConfig/BMU-18S_APP_STM32F103CB_1.0.0.dbgconf
Normal file
36
USER/DebugConfig/BMU-18S_APP_STM32F103CB_1.0.0.dbgconf
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@@ -0,0 +1,36 @@
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// File: STM32F101_102_103_105_107.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
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// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
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||||
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||||
// <<< Use Configuration Wizard in Context Menu >>>
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||||
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||||
// <h> Debug MCU configuration register (DBGMCU_CR)
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// <i> Reserved bits must be kept at reset value
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||||
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
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// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
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// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
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// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
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// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
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// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
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// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
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// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
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// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
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// <o.2> DBG_STANDBY <i> Debug standby mode
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// <o.1> DBG_STOP <i> Debug stop mode
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// <o.0> DBG_SLEEP <i> Debug sleep mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <<< end of configuration section >>>
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36
USER/DebugConfig/BMU-20S_APP_STM32F103CB_1.0.0.dbgconf
Normal file
36
USER/DebugConfig/BMU-20S_APP_STM32F103CB_1.0.0.dbgconf
Normal file
@@ -0,0 +1,36 @@
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||||
// File: STM32F101_102_103_105_107.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
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// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
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||||
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||||
// <<< Use Configuration Wizard in Context Menu >>>
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||||
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <i> Reserved bits must be kept at reset value
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// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
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// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
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// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
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// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
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// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
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// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
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// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
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// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
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// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
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// <o.2> DBG_STANDBY <i> Debug standby mode
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// <o.1> DBG_STOP <i> Debug stop mode
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// <o.0> DBG_SLEEP <i> Debug sleep mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <<< end of configuration section >>>
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36
USER/DebugConfig/BMU_20S_APP_STM32F103CB_1.0.0.dbgconf
Normal file
36
USER/DebugConfig/BMU_20S_APP_STM32F103CB_1.0.0.dbgconf
Normal file
@@ -0,0 +1,36 @@
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||||
// File: STM32F101_102_103_105_107.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
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// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
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||||
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||||
// <<< Use Configuration Wizard in Context Menu >>>
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||||
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||||
// <h> Debug MCU configuration register (DBGMCU_CR)
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// <i> Reserved bits must be kept at reset value
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||||
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
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// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
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// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
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// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
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// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
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// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
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// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
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// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
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// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
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// <o.2> DBG_STANDBY <i> Debug standby mode
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// <o.1> DBG_STOP <i> Debug stop mode
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// <o.0> DBG_SLEEP <i> Debug sleep mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <<< end of configuration section >>>
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||||
36
USER/DebugConfig/BMU_21S_APP_STM32F103CB_1.0.0.dbgconf
Normal file
36
USER/DebugConfig/BMU_21S_APP_STM32F103CB_1.0.0.dbgconf
Normal file
@@ -0,0 +1,36 @@
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||||
// File: STM32F101_102_103_105_107.dbgconf
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||||
// Version: 1.0.0
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||||
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
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||||
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
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||||
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||||
// <<< Use Configuration Wizard in Context Menu >>>
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||||
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||||
// <h> Debug MCU configuration register (DBGMCU_CR)
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||||
// <i> Reserved bits must be kept at reset value
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||||
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
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||||
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
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||||
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
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||||
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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||||
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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||||
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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||||
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
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||||
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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||||
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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||||
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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||||
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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||||
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
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||||
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
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||||
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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||||
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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||||
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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||||
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
|
||||
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
|
||||
// <o.2> DBG_STANDBY <i> Debug standby mode
|
||||
// <o.1> DBG_STOP <i> Debug stop mode
|
||||
// <o.0> DBG_SLEEP <i> Debug sleep mode
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||||
// </h>
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||||
DbgMCU_CR = 0x00000007;
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||||
|
||||
// <<< end of configuration section >>>
|
||||
48
USER/DebugConfig/mBMS-16S_APP_STM32F407VGTx.dbgconf
Normal file
48
USER/DebugConfig/mBMS-16S_APP_STM32F407VGTx.dbgconf
Normal file
@@ -0,0 +1,48 @@
|
||||
// File: STM32F405_415_407_417_427_437_429_439.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
|
||||
// refer to STM32F40x STM32F41x datasheets
|
||||
// refer to STM32F42x STM32F43x datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <o.2> DBG_STANDBY <i> Debug Standby Mode
|
||||
// <o.1> DBG_STOP <i> Debug Stop Mode
|
||||
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
|
||||
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
|
||||
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
|
||||
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
|
||||
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
|
||||
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
|
||||
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB1_Fz = 0x00000000;
|
||||
|
||||
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB2_Fz = 0x00000000;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
36
USER/DebugConfig/mBMS-18S_APP_STM32F103CB_1.0.0.dbgconf
Normal file
36
USER/DebugConfig/mBMS-18S_APP_STM32F103CB_1.0.0.dbgconf
Normal file
@@ -0,0 +1,36 @@
|
||||
// File: STM32F101_102_103_105_107.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
|
||||
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
|
||||
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
|
||||
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
|
||||
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
|
||||
// <o.2> DBG_STANDBY <i> Debug standby mode
|
||||
// <o.1> DBG_STOP <i> Debug stop mode
|
||||
// <o.0> DBG_SLEEP <i> Debug sleep mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
48
USER/DebugConfig/mBMS-18S_APP_STM32F407VGTx.dbgconf
Normal file
48
USER/DebugConfig/mBMS-18S_APP_STM32F407VGTx.dbgconf
Normal file
@@ -0,0 +1,48 @@
|
||||
// File: STM32F405_415_407_417_427_437_429_439.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
|
||||
// refer to STM32F40x STM32F41x datasheets
|
||||
// refer to STM32F42x STM32F43x datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <o.2> DBG_STANDBY <i> Debug Standby Mode
|
||||
// <o.1> DBG_STOP <i> Debug Stop Mode
|
||||
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
|
||||
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
|
||||
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
|
||||
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
|
||||
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
|
||||
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
|
||||
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB1_Fz = 0x00000000;
|
||||
|
||||
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB2_Fz = 0x00000000;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
48
USER/DebugConfig/mBMS_APP_STM32F407VGTx.dbgconf
Normal file
48
USER/DebugConfig/mBMS_APP_STM32F407VGTx.dbgconf
Normal file
@@ -0,0 +1,48 @@
|
||||
// File: STM32F405_415_407_417_427_437_429_439.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
|
||||
// refer to STM32F40x STM32F41x datasheets
|
||||
// refer to STM32F42x STM32F43x datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <o.2> DBG_STANDBY <i> Debug Standby Mode
|
||||
// <o.1> DBG_STOP <i> Debug Stop Mode
|
||||
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
|
||||
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
|
||||
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
|
||||
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
|
||||
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
|
||||
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
|
||||
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
|
||||
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB1_Fz = 0x00000000;
|
||||
|
||||
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// </h>
|
||||
DbgMCU_APB2_Fz = 0x00000000;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
Reference in New Issue
Block a user