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feat: KT mBMS 펌웨어 3종(HW1/2/3) 및 통합 빌드 환경 초기 커밋 (V4.0.0.1)

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jkwoo
2026-11-05 14:31:31 +09:00
commit c52dc2f348
10803 changed files with 4642514 additions and 0 deletions
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1
mBMS_APP_V3117/USER/CopyHex_Flash.bat Normal file
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copy Flash\Obj\mBMS_APP.hex Flash\mBMS_APP_V4001.hex

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mBMS_APP_V3117/USER/DebugConfig/BMCB_APP_STM32F407VGTx.dbgconf Normal file
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// <<< Use Configuration Wizard in Context Menu >>>
// <h>Debug MCU Configuration
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
// <o.1> DBG_STOP <i> Debug Stop Mode
// <o.2> DBG_STANDBY <i> Debug Standby Mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 Freeze
// <o.0> DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
// <o.1> DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
// <o.2> DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
// <o.3> DBG_TIM5_STOP <i> Timer 5 Stopped when Core is halted
// <o.4> DBG_TIM6_STOP <i> Timer 6 Stopped when Core is halted
// <o.5> DBG_TIM7_STOP <i> Timer 7 Stopped when Core is halted
// <o.6> DBG_TIM12_STOP <i> Timer 12 Stopped when Core is halted
// <o.7> DBG_TIM13_STOP <i> Timer 13 Stopped when Core is halted
// <o.8> DBG_TIM14_STOP <i> Timer 14 Stopped when Core is halted
// <o.10> DBG_RTC_STOP <i> RTC Stopped when Core is halted
// <o.11> DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
// <o.12> DBG_IWDG_STOP <i> Independent Watchdog Stopped when Core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS Timeout Mode Stopped when Core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS Timeout Mode Stopped when Core is halted
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS Timeout Mode Stopped when Core is halted
// <o.25> DBG_CAN1_STOP <i> CAN1 Stopped when Core is halted
// <o.26> DBG_CAN2_STOP <i> CAN2 Stopped when Core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 Freeze
// <o.0> DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
// <o.1> DBG_TIM8_STOP <i> Timer 8 Stopped when Core is halted
// <o.16> DBG_TIM9_STOP <i> Timer 9 Stopped when Core is halted
// <o.17> DBG_TIM10_STOP <i> Timer 10 Stopped when Core is halted
// <o.18> DBG_TIM11_STOP <i> Timer 11 Stopped when Core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <<< end of configuration section >>>

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mBMS_APP_V3117/USER/DebugConfig/mBMS-16S_APP_STM32F407VGTx.dbgconf Normal file
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// File: STM32F405_415_407_417_427_437_429_439.dbgconf
// Version: 1.0.0
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
// refer to STM32F40x STM32F41x datasheets
// refer to STM32F42x STM32F43x datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <o.2> DBG_STANDBY <i> Debug Standby Mode
// <o.1> DBG_STOP <i> Debug Stop Mode
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <<< end of configuration section >>>

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mBMS_APP_V3117/USER/DebugConfig/mBMS_APP_STM32F407VGTx.dbgconf Normal file
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// File: STM32F405_415_407_417_427_437_429_439.dbgconf
// Version: 1.0.0
// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
// refer to STM32F40x STM32F41x datasheets
// refer to STM32F42x STM32F43x datasheets
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU configuration register (DBGMCU_CR)
// <o.2> DBG_STANDBY <i> Debug Standby Mode
// <o.1> DBG_STOP <i> Debug Stop Mode
// <o.0> DBG_SLEEP <i> Debug Sleep Mode
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
// <i> Reserved bits must be kept at reset value
// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
// <i> Reserved bits must be kept at reset value
// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <<< end of configuration section >>>

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mBMS_APP_V3117/USER/Hex2Bin_Flash.bat Normal file
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hex2bin.exe -b .\FLASH\mBMS_APP_V4001.hex

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mBMS_APP_V3117/USER/JLinkSettings___.ini Normal file
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[BREAKPOINTS]
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="UNSPECIFIED"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

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mBMS_APP_V3117/USER/build_log.txt Normal file
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*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Build target 'mBMS-16S_APP'
compiling can_data_process.c...
linking...
Program Size: Code=65194 RO-data=3322 RW-data=552 ZI-data=119248
FromELF: creating hex file...
After Build - User command #1: CopyHex_Flash.bat
d:\Project\Firmware\KT\mBMS\R4xx\mBMS_APP_V3117\USER>copy Flash\Obj\mBMS_APP.hex Flash\mBMS_APP_V4001.hex
1개 파일이 복사되었습니다.
After Build - User command #2: Hex2Bin_Flash.bat
d:\Project\Firmware\KT\mBMS\R4xx\mBMS_APP_V3117\USER>hex2bin.exe -b .\FLASH\mBMS_APP_V4001.hex
hex2bin v2.1, Copyright (C) 2015 Jacques Pelletier & contributors
Lowest address: 134348800
Highest address: 134417383
Starting address: 134348800
Max Length: 68584
Binary file start = 08020000
Records start = 08020000
Highest address = 08030BE7
Pad Byte = FF
".\FLASH\obj\mBMS_APP.axf" - 0 Error(s), 0 Warning(s).
Build Time Elapsed: 00:00:02

BIN
mBMS_APP_V3117/USER/hex2bin.exe Normal file
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Binary file not shown.

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mBMS_APP_V3117/USER/lwipopts.h Normal file
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/**
******************************************************************************
* @file LwIP/LwIP_IAP/Inc/lwipopts.h
* @author MCD Application Team
* @version V1.2.0
* @date 26-December-2014
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
#ifndef __LWIPOPTS_H__
#define __LWIPOPTS_H__
/**
* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
* critical regions during buffer allocation, deallocation and memory
* allocation and deallocation.
*/
#define SYS_LIGHTWEIGHT_PROT 0
/**
* NO_SYS==1: Provides VERY minimal functionality. Otherwise,
* use lwIP facilities.
*/
#define NO_SYS 1
/* ---------- Memory options ---------- */
/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
byte alignment -> define MEM_ALIGNMENT to 2. */
#define MEM_ALIGNMENT 4
/* MEM_SIZE: the size of the heap memory. If the application will send
a lot of data that needs to be copied, this should be set high. */
#define MEM_SIZE (30*1024)
/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
sends a lot of data out of ROM (or other static memory), this
should be set high. */
#define MEMP_NUM_PBUF 10
/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
per active UDP "connection". */
#define MEMP_NUM_UDP_PCB 6
/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
connections. */
#define MEMP_NUM_TCP_PCB 10
/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
connections. */
#define MEMP_NUM_TCP_PCB_LISTEN 6
/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
segments. */
#define MEMP_NUM_TCP_SEG 12
/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
timeouts. */
#define MEMP_NUM_SYS_TIMEOUT 10
/* ---------- Pbuf options ---------- */
/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
#define PBUF_POOL_SIZE 10
/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
#define PBUF_POOL_BUFSIZE 1524
/* ---------- TCP options ---------- */
#define LWIP_TCP 1
#define TCP_TTL 255
/* Controls if TCP should queue segments that arrive out of
order. Define to 0 if your device is low on memory. */
#define TCP_QUEUE_OOSEQ 0
/* TCP Maximum segment size. */
#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */
/* TCP sender buffer space (bytes). */
#define TCP_SND_BUF (4*TCP_MSS)
/* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. */
#define TCP_SND_QUEUELEN (2* TCP_SND_BUF/TCP_MSS)
/* TCP receive window. */
#define TCP_WND (2*TCP_MSS)
/* ---------- ICMP options ---------- */
#define LWIP_ICMP 1
/* ---------- DHCP options ---------- */
/* Define LWIP_DHCP to 1 if you want DHCP configuration of
interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
turning this on does currently not work. */
#define LWIP_DHCP 1
/* ---------- UDP options ---------- */
#define LWIP_UDP 1
#define UDP_TTL 255
/* ---------- Statistics options ---------- */
#define LWIP_STATS 0
#define LWIP_PROVIDE_ERRNO 1
/* ---------- link callback options ---------- */
/* LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
* whenever the link changes (i.e., link down)
*/
#define LWIP_NETIF_LINK_CALLBACK 1
/*
--------------------------------------
---------- Checksum options ----------
--------------------------------------
*/
/*
The STM32F4x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums by hardware:
- To use this feature let the following define uncommented.
- To disable it and process by CPU comment the the checksum.
*/
#define CHECKSUM_BY_HARDWARE
#ifdef CHECKSUM_BY_HARDWARE
/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 0
/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 0
/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 0
/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 0
/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 0
/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 0
/* CHECKSUM_CHECK_ICMP==0: Check checksums by hardware for incoming ICMP packets.*/
#define CHECKSUM_GEN_ICMP 0
#else
/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 1
/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 1
/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 1
/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 1
/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 1
/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 1
/* CHECKSUM_CHECK_ICMP==1: Check checksums by hardware for incoming ICMP packets.*/
#define CHECKSUM_GEN_ICMP 1
#endif
/*
----------------------------------------------
---------- Sequential layer options ----------
----------------------------------------------
*/
/**
* LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
*/
#define LWIP_NETCONN 0
/*
------------------------------------
---------- Socket options ----------
------------------------------------
*/
/**
* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
*/
#define LWIP_SOCKET 0
/*
----------------------------------------
---------- Lwip Debug options ----------
----------------------------------------
*/
//#define LWIP_DEBUG LWIP_DBG_ON
//#define SNMP_MIB_DEBUG LWIP_DBG_ON
//#define SNMP_MSG_DEBUG LWIP_DBG_ON
#define LWIP_SNMP 1
#define SNMP_PRIVATE_MIB 1
#endif /* __LWIPOPTS_H__ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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mBMS_APP_V3117/USER/mBMS_APP.uvprojx Normal file
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mBMS_APP_V3117/USER/main.c Normal file
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/**
******************************************************************************
* File Name : main.c
* Description : This file provides code for the configuration
* of main.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "sys.h"
#include "delay.h"
#include "usart.h"
#include "led.h"
#include "console.h"
#include "vi.h"
#include "temp.h"
#include "io.h"
#include "brtc.h"
#include "device_param.h"
#include "pl455_comm.h"
#include "can_comm.h"
#include "rs485_comm.h"
#include "log.h"
#include "task_manager.h"
#include "includes.h"
void console_task(void *p_arg);
//Task priority
#define START_TASK_PRIO 3
//Task stack size
#define START_STK_SIZE 512
//Task stack
CPU_STK START_TASK_STK[START_STK_SIZE];
//Task functions
void start_task(void *p_arg);
//can_comm task
//Task priority
#define CAN_COMM_TASK_PRIO 4
//Task stack size
#define CAN_COMM_STK_SIZE 256
//Task stack
CPU_STK CAN_COMM_TASK_STK[CAN_COMM_STK_SIZE];
//Task functions
void can_comm_task(void *p_arg);
//PL455 comm task
//Task priority
#define PL455_COMM_TASK_PRIO 5
//Task stack size
#define PL455_COMM_STK_SIZE 256
//Task stack
CPU_STK PL455_COMM_TASK_STK[PL455_COMM_STK_SIZE];
//Task functions
void pl455_comm_task(void *p_arg);
//VI ADC task
//Task priority
#define VI_ADC_TASK_PRIO 6
//Task stack size
#define VI_ADC_STK_SIZE 256
//Task stack
CPU_STK VI_ADC_TASK_STK[VI_ADC_STK_SIZE];
//Task functions
void vi_adc_task(void *p_arg);
//TEMP task
//Task priority
#define TEMP_TASK_PRIO 7
//Task stack size
#define TEMP_STK_SIZE 256
//Task stack
CPU_STK TEMP_TASK_STK[TEMP_STK_SIZE];
//Task functions
void temp_task(void *p_arg);
//RS485 task
//Task priority
#define RS485_COMM_TASK_PRIO 8
//Task stack size
#define RS485_COMM_STK_SIZE 128
//Task stack
CPU_STK RS485_COMM_TASK_STK[RS485_COMM_STK_SIZE];
//Task functions
void rs485_comm_task(void *p_arg);
//io task
//Task priority
#define IO_TASK_PRIO 9
//Task stack size
#define IO_STK_SIZE 128
//Task stack
CPU_STK IO_TASK_STK[IO_STK_SIZE];
//Task functions
void io_task(void *p_arg);
////log task
////Task priority
//#define LOG_TASK_PRIO 10
////Task stack size
//#define LOG_STK_SIZE 2048
////Task control block
//OS_TCB LOGTaskTCB;
////Task stack
//CPU_STK LOG_TASK_STK[LOG_STK_SIZE];
////Task functions
//void log_task(void *p_arg);
OS_Q snmp_trapQ;
int main(void)
{
OS_ERR err;
CPU_SR_ALLOC();
delay_init(168); // Delay init
bsp_Init();
TaksTCBInit();
OSInit(&err); // UCOSIII init
OS_CRITICAL_ENTER(); // Enter critical section
//Create a started task
OSTaskCreate((OS_TCB * )GetAppTaskTCB(START_TASK_PRIO), //Task control block
(CPU_CHAR * )"Start Task", //Task name
(OS_TASK_PTR )start_task, //Task functions
(void * )0, //The parameters passed to the task function
(OS_PRIO )START_TASK_PRIO, //Task priority
(CPU_STK * )&START_TASK_STK[0], //Task stack base address
(CPU_STK_SIZE)START_STK_SIZE/10, //Task stack depth limit
(CPU_STK_SIZE)START_STK_SIZE, //Task stack size
(OS_MSG_QTY )0, //Tasks within the maximum number of messages that Message Queuing can receive, for the 0 o'clock to receive messages
(OS_TICK )0, //When enabling Web time length, is 0 for the default length£¬
(void * )0, //Users add stores
(OS_OPT )OS_OPT_TASK_STK_CHK|OS_OPT_TASK_STK_CLR, //Task options
(OS_ERR * )&err); //Store the return value of the function when an error
OS_CRITICAL_EXIT(); //Exit the critical section
OSStart(&err); //Start UCOSIII
while(1);
}
//Start task functions
void start_task(void *p_arg)
{
OS_ERR err;
CPU_SR_ALLOC();
p_arg = p_arg;
CPU_Init();
#if OS_CFG_STAT_TASK_EN > 0u
OSStatTaskCPUUsageInit(&err); //Statistical tasks
#endif
#ifdef CPU_CFG_INT_DIS_MEAS_EN //If measurement is enabled interrupt off time
CPU_IntDisMeasMaxCurReset();
#endif
#if OS_CFG_SCHED_ROUND_ROBIN_EN //When you use the Web when
//The time slice round robin feature, the length of the time slice to 1 system clock ticks, 1*5=5ms
OSSchedRoundRobinCfg(DEF_ENABLED,1,&err);
#endif
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_CRC,ENABLE);//Enable the CRC clock
OS_CRITICAL_ENTER(); //Enters the critical section
// CAN Comm Task
OSTaskCreate((OS_TCB* )GetAppTaskTCB(CAN_COMM_TASK_PRIO),
(CPU_CHAR* )"CAN Comm Task",
(OS_TASK_PTR )can_comm_task,
(void* )0,
(OS_PRIO )CAN_COMM_TASK_PRIO,
(CPU_STK* )&CAN_COMM_TASK_STK[0],
(CPU_STK_SIZE)CAN_COMM_STK_SIZE/10,
(CPU_STK_SIZE)CAN_COMM_STK_SIZE,
(OS_MSG_QTY )0,
(OS_TICK )0,
(void* )0,
(OS_OPT )OS_OPT_TASK_STK_CHK|OS_OPT_TASK_STK_CLR,
(OS_ERR* )&err);
// PL455 Comm task
OSTaskCreate((OS_TCB* )GetAppTaskTCB(PL455_COMM_TASK_PRIO),
(CPU_CHAR* )"PL455 Comm Task",
(OS_TASK_PTR )pl455_comm_task,
(void* )0,
(OS_PRIO )PL455_COMM_TASK_PRIO,
(CPU_STK* )&PL455_COMM_TASK_STK[0],
(CPU_STK_SIZE)PL455_COMM_STK_SIZE/10,
(CPU_STK_SIZE)PL455_COMM_STK_SIZE,
(OS_MSG_QTY )0,
(OS_TICK )0,
(void* )0,
(OS_OPT )OS_OPT_TASK_STK_CHK|OS_OPT_TASK_STK_CLR,
(OS_ERR* )&err);
//VI ADC task
OSTaskCreate((OS_TCB* )GetAppTaskTCB(VI_ADC_TASK_PRIO),
(CPU_CHAR* )"VI ADC Task",
(OS_TASK_PTR )vi_adc_task,
(void* )0,
(OS_PRIO )VI_ADC_TASK_PRIO,
(CPU_STK* )&VI_ADC_TASK_STK[0],
(CPU_STK_SIZE)VI_ADC_STK_SIZE/10,
(CPU_STK_SIZE)VI_ADC_STK_SIZE,
(OS_MSG_QTY )0,
(OS_TICK )0,
(void* )0,
(OS_OPT )OS_OPT_TASK_STK_CHK|OS_OPT_TASK_STK_CLR,
(OS_ERR* )&err);
//Temp ADC task
OSTaskCreate((OS_TCB* )GetAppTaskTCB(TEMP_TASK_PRIO),
(CPU_CHAR* )"Temp ADC Task",
(OS_TASK_PTR )temp_task,
(void* )0,
(OS_PRIO )TEMP_TASK_PRIO,
(CPU_STK* )&TEMP_TASK_STK[0],
(CPU_STK_SIZE)TEMP_STK_SIZE/10,
(CPU_STK_SIZE)TEMP_STK_SIZE,
(OS_MSG_QTY )0,
(OS_TICK )0,
(void* )0,
(OS_OPT )OS_OPT_TASK_STK_CHK|OS_OPT_TASK_STK_CLR,
(OS_ERR* )&err);
//RS485 Comm Task
OSTaskCreate((OS_TCB* )GetAppTaskTCB(RS485_COMM_TASK_PRIO),
(CPU_CHAR* )"RS485 Comm Task",
(OS_TASK_PTR )rs485_comm_task,
(void* )0,
(OS_PRIO )RS485_COMM_TASK_PRIO,
(CPU_STK* )&RS485_COMM_TASK_STK[0],
(CPU_STK_SIZE)RS485_COMM_STK_SIZE/10,
(CPU_STK_SIZE)RS485_COMM_STK_SIZE,
(OS_MSG_QTY )0,
(OS_TICK )0,
(void* )0,
(OS_OPT )OS_OPT_TASK_STK_CHK|OS_OPT_TASK_STK_CLR,
(OS_ERR* )&err);
//IO Task
OSTaskCreate((OS_TCB* )GetAppTaskTCB(IO_TASK_PRIO),
(CPU_CHAR* )"IO task",
(OS_TASK_PTR )io_task,
(void* )0,
(OS_PRIO )IO_TASK_PRIO,
(CPU_STK* )&IO_TASK_STK[0],
(CPU_STK_SIZE)IO_STK_SIZE/10,
(CPU_STK_SIZE)IO_STK_SIZE,
(OS_MSG_QTY )0,
(OS_TICK )0,
(void* )0,
(OS_OPT )OS_OPT_TASK_STK_CHK|OS_OPT_TASK_STK_CLR,
(OS_ERR* )&err);
//Log Task
// OSTaskCreate((OS_TCB* )&LOGTaskTCB,
// (CPU_CHAR* )"LOG task",
// (OS_TASK_PTR )log_task,
// (void* )0,
// (OS_PRIO )LOG_TASK_PRIO,
// (CPU_STK* )&LOG_TASK_STK[0],
// (CPU_STK_SIZE)LOG_STK_SIZE/10,
// (CPU_STK_SIZE)LOG_STK_SIZE,
// (OS_MSG_QTY )0,
// (OS_TICK )0,
// (void* )0,
// (OS_OPT )OS_OPT_TASK_STK_CHK|OS_OPT_TASK_STK_CLR,
// (OS_ERR* )&err);
//Trap Task
// OSTaskCreate((OS_TCB* )GetAppTaskTCB(TRAP_TASK_PRIO),
// (CPU_CHAR* )"Trap task",
// (OS_TASK_PTR )trap_task,
// (void* )0,
// (OS_PRIO )TRAP_TASK_PRIO,
// (CPU_STK* )&TRAP_TASK_STK[0],
// (CPU_STK_SIZE)TRAP_STK_SIZE/10,
// (CPU_STK_SIZE)TRAP_STK_SIZE,
// (OS_MSG_QTY )0,
// (OS_TICK )0,
// (void* )0,
// (OS_OPT )OS_OPT_TASK_STK_CHK|OS_OPT_TASK_STK_CLR,
// (OS_ERR* )&err);
//
OS_TaskSuspend((OS_TCB*)GetAppTaskTCB(START_TASK_PRIO),&err); //Pending start task
OS_CRITICAL_EXIT(); //Exit the critical section
console_task(p_arg);
}
//Console Task
void console_task(void *p_arg)
{
AppTaskDebug();
}
//CAN COMM Task
void can_comm_task(void *p_arg)
{
App_TaskCanComm();
}
//PL455 COMM Task
void pl455_comm_task(void *p_arg)
{
App_TaskPl455Comm();
}
//VI Adc Task
void vi_adc_task(void *p_arg)
{
AppTaskVIAdc();
}
//Temp Task
void temp_task(void *p_arg)
{
AppTaskTempAdc();
}
//IO Task
void rs485_comm_task(void *p_arg)
{
App_TaskRs485Comm();
}
//IO Task
void io_task(void *p_arg)
{
App_TaskIO();
}
////LCD COMM Task
//void lcd_comm_task(void *p_arg)
//{
// App_TaskLcdComm();
//}
//LOG Task
void log_task(void *p_arg)
{
// while(1)
// {
// }
}

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/**
******************************************************************************
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief Library configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_CONF_H
#define __STM32F4xx_CONF_H
/* Includes ------------------------------------------------------------------*/
/* Uncomment the line below to enable peripheral header file inclusion */
#include "stm32f4xx_adc.h"
#include "stm32f4xx_crc.h"
#include "stm32f4xx_dbgmcu.h"
#include "stm32f4xx_dma.h"
#include "stm32f4xx_exti.h"
#include "stm32f4xx_flash.h"
#include "stm32f4xx_gpio.h"
#include "stm32f4xx_i2c.h"
#include "stm32f4xx_iwdg.h"
#include "stm32f4xx_pwr.h"
#include "stm32f4xx_rcc.h"
#include "stm32f4xx_rtc.h"
#include "stm32f4xx_sdio.h"
#include "stm32f4xx_spi.h"
#include "stm32f4xx_syscfg.h"
#include "stm32f4xx_tim.h"
#include "stm32f4xx_usart.h"
#include "stm32f4xx_wwdg.h"
#include "stm32f4xx_can.h"
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
#if defined (STM32F429_439xx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma2d.h"
#include "stm32f4xx_fmc.h"
#include "stm32f4xx_ltdc.h"
#include "stm32f4xx_sai.h"
#endif /* STM32F429_439xx */
#if defined (STM32F427_437xx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma2d.h"
#include "stm32f4xx_fmc.h"
#include "stm32f4xx_sai.h"
#endif /* STM32F427_437xx */
#if defined (STM32F40_41xxx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_fsmc.h"
#endif /* STM32F40_41xxx */
#if defined (STM32F411xE)
#include "stm32f4xx_flash_ramfunc.h"
#endif /* STM32F411xE */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* If an external clock source is used, then the value of the following define
should be set to the value of the external clock source, else, if no external
clock is used, keep this define commented */
/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT 1 */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* __STM32F4xx_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_it.c
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief Main Interrupt Service Routines.
* This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_it.h"
/** @addtogroup Template_Project
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/******************************************************************************/
/* Cortex-M4 Processor Exceptions Handlers */
/******************************************************************************/
/**
* @brief This function handles NMI exception.
* @param None
* @retval None
*/
void NMI_Handler(void)
{
}
/**
* @brief This function handles Hard Fault exception.
* @param None
* @retval None
*/
void HardFault_Handler(void)
{
/* Go to infinite loop when Hard Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Memory Manage exception.
* @param None
* @retval None
*/
void MemManage_Handler(void)
{
/* Go to infinite loop when Memory Manage exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Bus Fault exception.
* @param None
* @retval None
*/
void BusFault_Handler(void)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Usage Fault exception.
* @param None
* @retval None
*/
void UsageFault_Handler(void)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles SVCall exception.
* @param None
* @retval None
*/
void SVC_Handler(void)
{
}
/**
* @brief This function handles Debug Monitor exception.
* @param None
* @retval None
*/
void DebugMon_Handler(void)
{
}
/**
* @brief This function handles PendSVC exception.
* @param None
* @retval None
*/
//void PendSV_Handler(void)
//{
//}
/**
* @brief This function handles SysTick Handler.
* @param None
* @retval None
*/
//void SysTick_Handler(void)
//{
//
//}
/******************************************************************************/
/* STM32F4xx Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
/* available peripheral interrupt handler's name please refer to the startup */
/* file (startup_stm32f4xx.s). */
/******************************************************************************/
/**
* @brief This function handles PPP interrupt request.
* @param None
* @retval None
*/
/*void PPP_IRQHandler(void)
{
}*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_it.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_IT_H
#define __STM32F4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE. * * This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels
*
*/
/* lwIP includes. */
#include "lwip/debug.h"
#include "lwip/def.h"
#include "lwip/sys.h"
#include "lwip/mem.h"
#include "lpc_arch.h"
#include "app_cfg.h"
#include
#if NO_SYS==0
/* ------------------------ System architecture includes ----------------------------- */
#include "arch/sys_arch.h"
/* ------------------------ lwIP includes --------------------------------- */
#include "lwip/opt.h"
#include "lwip/stats.h"
/*----------------------------------------------------------------------------*/
/* DEFINITIONS */
/*----------------------------------------------------------------------------*/
//#define OS_CFG_TICK_RATE_HZ 1000
/*----------------------------------------------------------------------------*/
/* VARIABLES */
/*----------------------------------------------------------------------------*/
//定义lwip线程所需要的资源
static OS_MEM StackMem;
const void * const pvNullPointer = (mem_ptr_t*)0xffffffff;
__align(4) CPU_STK LwIP_Task_Stk[LWIP_TASK_MAX*LWIP_STK_SIZE];
__align(4) CPU_INT08U LwIP_task_priopity_stask[LWIP_TASK_MAX];
OS_TCB LwIP_task_TCB[LWIP_TASK_MAX];
/*---------------------------------------------------------------------------
*
* prototypes dealing with mailbox
*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*
* Routine: sys_mbox_new ucosiii version
*---------------------------------------------------------------------------*
* Description:
* Creates a new mailbox
* Inputs:
* sys_mbox_t *pxMailBox -- Handle to new mailbox
* s32_t size -- Size of elements in the mailbox
* Outputs:
* err_t -- lwip error type
*---------------------------------------------------------------------------*/
err_t sys_mbox_new( sys_mbox_t *pxMailBox, s32_t size )
{
OS_ERR ucErr;
OSQCreate(pxMailBox,"LWIP queue", size, &ucErr); //debugging interface need to defined by user
if (ucErr == OS_ERR_NONE)
{
return ERR_OK;
}
return ERR_MEM;
}
/*---------------------------------------------------------------------------*
* Routine: sys_mbox_free ucosiii version
*---------------------------------------------------------------------------*
* Description: * Deallocates a mailbox. Flush message queue and the deallocate it
* different from freertos
* Inputs:
* sys_mbox_t *pxMailBox -- Handle of mailbox
*---------------------------------------------------------------------------*/
void sys_mbox_free( sys_mbox_t *pxMailBox )
{
OS_ERR ucErr;
//LWIP_ASSERT( "sys_mbox_free ", pxMailBox != SYS_MBOX_NULL ); //清空消息队列
OSQFlush(pxMailBox,& ucErr); OSQDel(pxMailBox, OS_OPT_DEL_ALWAYS, &ucErr);
//LWIP_ASSERT( "OSQDel ", ucErr == OS_ERR_NONE );
}
/*---------------------------------------------------------------------------*
* Routine: sys_mbox_post ucosiii version
*---------------------------------------------------------------------------*
* Description:
* Post the "pxMessageToPost" to the mailbox.
* Inputs:
* sys_mbox_t pxMailBox -- Handle of mailbox
* void *pxMessageToPost -- Pointer to data to post
*---------------------------------------------------------------------------*/
void sys_mbox_post( sys_mbox_t *pxMailBox, void *pxMessageToPost )
{
OS_ERR ucErr;
CPU_INT08U i=0; //消息指针为空，则指向一个默认的消息
if( pxMessageToPost == NULL )
pxMessageToPost = (void*)&pvNullPointer; /* try 10 times */
while(i<10){
OSQPost(pxMailBox, pxMessageToPost,sizeof(pxMessageToPost),OS_OPT_POST_ALL,&ucErr);
if(ucErr == OS_ERR_NONE) break;
i++;
OSTimeDly(5,OS_OPT_TIME_DLY,&ucErr);
}
//LWIP_ASSERT( "sys_mbox_post error!\n", i !=10 );
}
/*---------------------------------------------------------------------------*
* Routine: sys_mbox_trypost ucosiii version
*---------------------------------------------------------------------------*
* Description:
* Try to post the "msg" to the mailbox. Returns immediately with
* error if cannot.
* Inputs:
* sys_mbox_t pxMailBox -- Handle of mailbox
* void *pxMessageToPost -- Pointer to data to post
* Outputs:
* err_t -- ERR_OK if message posted, else ERR_MEM
* if not.
*---------------------------------------------------------------------------*/
err_t sys_mbox_trypost( sys_mbox_t *pxMailBox, void *pxMessageToPost )
{
OS_ERR ucErr;
if(pxMessageToPost == NULL ) pxMessageToPost = (void*)&pvNullPointer;
OSQPost(pxMailBox, pxMessageToPost,sizeof(pxMessageToPost),OS_OPT_POST_ALL,&ucErr);
if(ucErr != OS_ERR_NONE){
return ERR_MEM;
}
return ERR_OK;
}
/*---------------------------------------------------------------------------*
* Routine: sys_arch_mbox_fetch ucosiii version
*---------------------------------------------------------------------------*
* Description:
* Blocks the thread until a message arrives in the mailbox, but does
* not block the thread longer than "timeout" milliseconds (similar to
* the sys_arch_sem_wait() function). The "msg" argument is a result
* parameter that is set by the function (i.e., by doing "*msg =
* ptr"). The "msg" parameter maybe NULL to indicate that the message
* should be dropped.
*
* The return values are the same as for the sys_arch_sem_wait() function:
* Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
* timeout.
*
* Note that a function with a similar name, sys_mbox_fetch(), is
* implemented by lwIP.
* Inputs:
* sys_mbox_t pxMailBox -- Handle of mailbox
* void **ppvBuffer -- Pointer to pointer to msg received
* u32_t ulTimeOut -- Number of milliseconds until timeout
* Outputs:
* u32_t -- SYS_ARCH_TIMEOUT if timeout, else number
* of milliseconds until received.
*---------------------------------------------------------------------------*/
u32_t sys_arch_mbox_fetch( sys_mbox_t *pxMailBox, void **ppvBuffer, u32_t ulTimeOut )
{
OS_ERR ucErr;
OS_MSG_SIZE msg_size;
CPU_TS ucos_timeout;
CPU_TS in_timeout = ulTimeOut/LWIP_ARCH_TICK_PER_MS;
if(ulTimeOut && in_timeout == 0)
in_timeout = 1;
ucos_timeout=0;
*ppvBuffer = OSQPend (pxMailBox,in_timeout,OS_OPT_PEND_BLOCKING,&msg_size, 0,&ucErr);
if ( ucErr == OS_ERR_TIMEOUT )
ucos_timeout = SYS_ARCH_TIMEOUT;
return ucos_timeout;
}
/*---------------------------------------------------------------------------*
* Routine: sys_arch_mbox_tryfetch usosiii version
*---------------------------------------------------------------------------*
* Description:
* Similar to sys_arch_mbox_fetch, but if message is not ready
* immediately, we'll return with SYS_MBOX_EMPTY. On success, 0 is
* returned.
* Inputs:
* sys_mbox_t mbox -- Handle of mailbox
* void **msg -- Pointer to pointer to msg received
* Outputs:
* u32_t -- SYS_MBOX_EMPTY if no messages. Otherwise,
* return ERR_OK.
* complementary:
* ucos中暂时没有相应的实现机制，暂时使用sys_arch_mbox_fetch实现
*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*
* Routine: sys_mbox_valid usosiii version
*---------------------------------------------------------------------------*
* Description:
* Check if an mbox is valid/allocated
* if success return 1
* Inputs:
* sys_mbox_t *pxMailBox -- Handle of mailbox
* Outputs: * s32_t -- 1 if valid. Otherwise return 0
*---------------------------------------------------------------------------*/
s32_t sys_mbox_valid(sys_mbox_t *pxMailBox)
{
if(pxMailBox->NamePtr)
return (strcmp(pxMailBox->NamePtr,"?Q"))? 1:0;
else
return 0;
}
/*---------------------------------------------------------------------------*
* Routine: sys_mbox_invalid usosiii version
*---------------------------------------------------------------------------*
* Description:
* Set an mbox invalid so that sys_mbox_valid returns 0
* Inputs:
* sys_mbox_t *pxMailBox -- Handle of mailbox
*---------------------------------------------------------------------------*/
void sys_mbox_set_invalid(sys_mbox_t *pxMailBox)
{
if(sys_mbox_valid(pxMailBox))
sys_mbox_free(pxMailBox);
}
/*---------------------------------------------------------------------------*
* prototypes dealing with semaphore
*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*
* Routine: sys_sem_new ucosiii version
*---------------------------------------------------------------------------*
* Description:
* Creates and returns a new semaphore. The "ucCount" argument specifies
* the initial state of the semaphore.
* NOTE: Currently this routine only creates counts of 1 or 0 * Inputs:
* sys_mbox_t mbox -- Handle of mailbox
* u8_t ucCount -- Initial ucCount of semaphore (1 or 0)
* Outputs:
* sys_sem_t -- Created semaphore or 0 if could not create.
*---------------------------------------------------------------------------*/
err_t sys_sem_new( sys_sem_t *pxSemaphore, u8_t ucCount )
{
OS_ERR ucErr;
OSSemCreate (pxSemaphore,"LWIP Sem",ucCount,&ucErr);
if(ucErr != OS_ERR_NONE ){
//LWIP_ASSERT("OSSemCreate ",ucErr == OS_ERR_NONE );
return ERR_MEM;
}
return ERR_OK;
}
/*---------------------------------------------------------------------------*
* Routine: sys_arch_sem_wait
*---------------------------------------------------------------------------*
* Description:
* Blocks the thread while waiting for the semaphore to be
* signaled. If the "timeout" argument is non-zero, the thread should
* only be blocked for the specified time (measured in * milliseconds).
*
* If the timeout argument is non-zero, the return value is the number of
* milliseconds spent waiting for the semaphore to be signaled. If the
* semaphore wasn't signaled within the specified time, the return value is
* SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
* (i.e., it was already signaled), the function may return zero.
*
* Notice that lwIP implements a function with a similar name,
* sys_sem_wait(), that uses the sys_arch_sem_wait() function.
* Inputs:
* sys_sem_t sem -- Semaphore to wait on
* u32_t timeout -- Number of milliseconds until timeout
* Outputs:
* u32_t -- Time elapsed or SYS_ARCH_TIMEOUT.
*---------------------------------------------------------------------------*/
u32_t sys_arch_sem_wait( sys_sem_t *pxSemaphore, u32_t ulTimeout )
{
OS_ERR ucErr;
CPU_TS ucos_timeout;
CPU_TS in_timeout = ulTimeout/LWIP_ARCH_TICK_PER_MS;
if(ulTimeout && in_timeout == 0)
in_timeout = 1;
//OSSemPend (pxSemaphore,in_timeout,OS_OPT_PEND_BLOCKING,0,&ucErr);
//OSSemPend (pxSemaphore,ulTimeout,OS_OPT_PEND_BLOCKING,0,&ucErr);
OSSemPend (pxSemaphore,0,OS_OPT_PEND_BLOCKING,0,&ucErr); /* only when timeout! */
if(ucErr == OS_ERR_TIMEOUT)
ucos_timeout = SYS_ARCH_TIMEOUT;
return ucos_timeout;
}
/*---------------------------------------------------------------------------*
* Routine: sys_mutex_new ucosiii version
*---------------------------------------------------------------------------*
* Description:
* Creates and returns a new Mutex.
* Inputs:
* sys_mutex_t pxMutex -- Handle of mailbox
* Outputs:
* sys_mutex_t -- Created semaphore or 0 if could not create.
*---------------------------------------------------------------------------*/
err_t sys_mutex_new( sys_mutex_t *pxMutex )
{
OS_ERR ucErr;
OSMutexCreate(pxMutex,"LWIP Mutex",&ucErr);
if(ucErr != OS_ERR_NONE ){ //LWIP_ASSERT("OSMutexCreate ",ucErr == OS_ERR_NONE );
return ERR_MEM;
}
return ERR_OK;
}
/*---------------------------------------------------------------------------*
* Routine: sys_mutex_lock ucosiii version
*---------------------------------------------------------------------------*
* Description:
* Lock a mutex
* Inputs:
* sys_mutex_t pxMutex -- the mutex to lock
*---------------------------------------------------------------------------*/
void sys_mutex_lock( sys_mutex_t *pxMutex )
{
OS_ERR ucERR;
OSMutexPend(pxMutex,0,OS_OPT_POST_ALL,NULL,&ucERR);
}
/*---------------------------------------------------------------------------*
* Routine: sys_mutex_unlock ucosiii version
*---------------------------------------------------------------------------*
* Description:
* unLock a mutex
* Inputs:
* sys_mutex_t pxMutex -- the mutex to unlock
*---------------------------------------------------------------------------*/
void sys_mutex_unlock(sys_mutex_t *pxMutex )
{
OS_ERR ucERR;
OSMutexPost(pxMutex,OS_OPT_POST_NONE,&ucERR);
}
/*
* Delete a semaphore
* @param pxMutex the mutex to delete
*/
/*
void sys_mutex_free( sys_mutex_t *pxMutex )
{
OS_ERR ucERR;
OSMutexDel(pxMutex,OS_OPT_DEL_ALWAYS,&ucERR);
}
*/
/*---------------------------------------------------------------------------*
* Routine: sys_sem_signal ucosiii version
*---------------------------------------------------------------------------*
* Description:
* Signals (releases) a semaphore
* Inputs:
* sys_sem_t pxSemaphore -- Semaphore to signal
*---------------------------------------------------------------------------*/
void sys_sem_signal( sys_sem_t *pxSemaphore )
{
OS_ERR ucErr;
OSSemPost(pxSemaphore,OS_OPT_POST_ALL,&ucErr);
//LWIP_ASSERT("OSSemPost ",ucErr == OS_ERR_NONE );
}
/*---------------------------------------------------------------------------*
* Routine: sys_sem_free ucosiii version
*---------------------------------------------------------------------------*
* Description:
* Deallocates a semaphore
* Inputs:
* sys_sem_t pxSemaphore -- Semaphore to free
*---------------------------------------------------------------------------*/
void sys_sem_free( sys_sem_t *pxSemaphore )
{
OS_ERR ucErr;
OSSemDel(pxSemaphore, OS_OPT_DEL_ALWAYS, &ucErr );
//LWIP_ASSERT( "OSSemDel ", ucErr == OS_ERR_NONE );
}
/*---------------------------------------------------------------------------*
* Routine: sys_sem_valid usosiii version
*---------------------------------------------------------------------------*
* Description:
* Check if an mbox is valid/allocated
* if success return 1
* Inputs:
* sys_mbox_t *pxSemaphore -- Handle of mailbox
* Outputs:
* s32_t -- 1 if valid. Otherwise return 0
*---------------------------------------------------------------------------*/
s32_t sys_sem_valid(sys_sem_t *pxSemaphore)
{
if(pxSemaphore->NamePtr)
return (strcmp(pxSemaphore->NamePtr,"?SEM"))? 1:0;
else
return 0;
}
/*---------------------------------------------------------------------------*
* Routine: sys_sem_set_invalid usosiii version
*---------------------------------------------------------------------------*
* Description:
* Set an mbox invalid so that sys_mbox_valid returns 0
* Inputs:
* sys_mbox_t *pxSemaphore -- Handle of mailbox
*---------------------------------------------------------------------------*/
void sys_sem_set_invalid(sys_sem_t *pxSemaphore)
{
if(sys_sem_valid(pxSemaphore)) sys_sem_free(pxSemaphore);
}
/*---------------------------------------------------------------------------*
* Routine: sys_init
*---------------------------------------------------------------------------*
* Description:
* Initialize sys arch
*---------------------------------------------------------------------------*/
void sys_init(void)
{
OS_ERR ucErr;
memset(LwIP_task_priopity_stask,0,sizeof(LwIP_task_priopity_stask));
/* init mem used by sys_mbox_t, use ucosIII functions */
OSMemCreate(&StackMem, "LWIP TASK STK", (void*)LwIP_Task_Stk,LWIP_TASK_MAX, LWIP_STK_SIZE*sizeof(CPU_STK), &ucErr);
//LWIP_ASSERT( "sys_init: failed OSMemCreate STK", ucErr == OS_ERR_NONE );
}
/*暂未使能ucosiii计时功能
u32_t sys_now(void)
{
return xTaskGetTickCount();
}
*/
/*---------------------------------------------------------------------------*
* Routine: sys_thread_new
*---------------------------------------------------------------------------*
* Description:
* Starts a new thread with priority "prio" that will begin its
* execution in the function "thread()". The "arg" argument will be
* passed as an argument to the thread() function. The id of the new
* thread is returned. Both the id and the priority are system
* dependent.
* Inputs:
* char *name -- Name of thread
* void (* thread)(void *arg) -- Pointer to function to run.
* void *arg -- Argument passed into function
* int stacksize -- Required stack amount in bytes
* int prio -- Thread priority
* Outputs:
* sys_thread_t -- Pointer to per-thread timeouts.
*---------------------------------------------------------------------------*/
sys_thread_t sys_thread_new( const char *name, void( *thread )( void *pvParameters ), void *arg, int stacksize, int prio )
{
CPU_INT08U ubPrio = LWIP_TASK_START_PRIO;
CPU_INT08U tsk_prio;
CPU_STK *task_stk;
OS_ERR ucErr;
static u32_t i = 0;
arg = arg;
/*1111
//确定task优先级
if(prio){
ubPrio +=(prio-1); //确认优先权数组中有无优先级为(LWIP_TASK_START_PRIO+prio-1)的数
for(i=0; i= (LWIP_TASK_START_PRIO+LWIP_TASK_MAX) || i == LWIP_TASK_MAX){
LWIP_ASSERT( "sys_thread_new: there is no free priority", 0 );
return (-1);
}
}
*/
//确定task堆栈值
if(stacksize > LWIP_STK_SIZE || !stacksize)
stacksize = LWIP_STK_SIZE;
/* get Stack from pool */
//
CPU_STK * task_stk = OSMemGet( &StackMem, &ucErr );
task_stk = OSMemGet( &StackMem, &ucErr );
if(ucErr != OS_ERR_NONE){
//LWIP_ASSERT( "sys_thread_new: impossible to get a stack", 0 );
return (-1);
}
if(i < 6){
tsk_prio = i;
i++;
}
else
return (-1); //
tsk_prio = ubPrio-LWIP_TASK_START_PRIO;
OSTaskCreate(&LwIP_task_TCB[tsk_prio],
(CPU_CHAR *)name,
(OS_TASK_PTR )thread,
(void *)arg,
(OS_PRIO )prio,
//ubPrio,
(CPU_STK *)&task_stk[0],
(CPU_STK_SIZE )stacksize/10,
(CPU_STK_SIZE )stacksize,
(OS_MSG_QTY )0,
(OS_TICK )0,
(void *)0,
(OS_OPT )(OS_OPT_TASK_STK_CHK | OS_OPT_TASK_STK_CLR),
(OS_ERR *)&ucErr);
return ubPrio;
//return ubPrio;
}
/*---------------------------------------------------------------------------*
* Routine: sys_arch_protect ucosiii version
*---------------------------------------------------------------------------*
* Description:
* This optional function does a "fast" critical region protection and
* returns the previous protection level. This function is only called
* during very short critical regions. An embedded system which supports
* ISR-based drivers might want to implement this function by disabling
* interrupts. Task-based systems might want to implement this by using
* a mutex or disabling tasking. This function should support recursive
* calls from the same task or interrupt. In other words,
* sys_arch_protect() could be called while already protected. In
* that case the return value indicates that it is already protected.
*
* sys_arch_protect() is only required if your port is supporting an
* operating system.
* Outputs:
* sys_prot_t -- Previous protection level (not used here)
*---------------------------------------------------------------------------*/
sys_prot_t sys_arch_protect( void )
{
CPU_SR cpu_sr;
OS_CRITICAL_ENTER();
return (( sys_prot_t )1);
}
/*---------------------------------------------------------------------------*
* Routine: sys_arch_unprotect ucosiii version
*---------------------------------------------------------------------------*
* Description:
* This optional function does a "fast" set of critical region
* protection to the value specified by pval. See the documentation for
* sys_arch_protect() for more information. This function is only
* required if your port is supporting an operating system.
* Inputs:
* sys_prot_t -- Previous protection level (not used here)
*---------------------------------------------------------------------------*/
void sys_arch_unprotect( sys_prot_t xValue )
{
CPU_SR cpu_sr;
OS_CRITICAL_EXIT();
}
/*
* Prints an assertion messages and aborts execution.
*/
/*
void sys_assert( const char *pcMessage )
{
(void) pcMessage;
for (;;) { }
}
*/
/** * @brief MilliSecond delay function based on FreeRTOS
* @param ms : Number of milliSeconds to delay
* @return Nothing
* Needed for some functions, do not use prior to FreeRTOS running
*/
void msDelay(CPU_INT32U ms)
{
OS_ERR ucErr;
OSTimeDly(ms, OS_OPT_TIME_DLY, &ucErr);
}
/*-------------------------------------------------------------------------*
* End of File: sys_arch.c
*-------------------------------------------------------------------------*/
#endif
/*-----------------------------------------------------------------------------------*/

554
mBMS_APP_V3117/USER/system_stm32f4xx.c Normal file
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@@ -0,0 +1,554 @@
/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 10-October-2011
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F4xx devices,
* and is generated by the clock configuration tool
* stm32f4xx_Clock_Configuration_V1.0.0.xls
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F4xx device revision | Rev A
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 168000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 168000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 336
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 7
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Main regulator output voltage | Scale1 mode
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 5
*-----------------------------------------------------------------------------
* Prefetch Buffer | OFF
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Enabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM324xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x20000 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/************************* PLL Parameters *************************************/
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 25
#define PLL_N 336
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 168000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @Note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
static void SetSysClock(void)
{
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f4xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external SRAM mounted on STM324xG_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
| PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
| PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
| PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
| | PE15 <-> FSMC_D12 |
+-------------------+--------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078;
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcc0ccccc;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xaaaa0a0a;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xffff0f0f;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xc00cc0cc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaa828a;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffc3cf;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010603;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 3;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 6;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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mBMS_APP_V3117/USER/system_stm32f4xx.h Normal file
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/**
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F4XX_H
#define __SYSTEM_STM32F4XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F4xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F4XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/