feat: KT mBMS 펌웨어 3종(HW1/2/3) 및 통합 빌드 환경 초기 커밋 (V4.0.0.1)

This commit is contained in:
2026-11-05 14:31:31 +09:00
commit c52dc2f348
10803 changed files with 4642514 additions and 0 deletions

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM1_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM1_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_ROM2_start__ = 0x03000C00;
define symbol __ICFEDIT_region_ROM2_end__ = 0x03000FFB;
define symbol __ICFEDIT_region_RAM1_start__ = 0x1FFF8000;
define symbol __ICFEDIT_region_RAM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_RAM2_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF;
define symbol __ICFEDIT_region_RAM3_start__ = 0x20010000;
define symbol __ICFEDIT_region_RAM3_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_RAM4_start__ = 0x20020000;
define symbol __ICFEDIT_region_RAM4_end__ = 0x20026FFF;
define symbol __ICFEDIT_region_RAM5_start__ = 0x200F0000;
define symbol __ICFEDIT_region_RAM5_end__ = 0x200F0FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__]
| mem:[from __ICFEDIT_region_ROM2_start__ to __ICFEDIT_region_ROM2_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]
| mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]
| mem:[from __ICFEDIT_region_RAM3_start__ to __ICFEDIT_region_RAM3_end__]
| mem:[from __ICFEDIT_region_RAM4_start__ to __ICFEDIT_region_RAM4_end__]
| mem:[from __ICFEDIT_region_RAM5_start__ to __ICFEDIT_region_RAM5_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
define symbol __ICFEDIT_region_IROM2_end__ = 0x03000FFB;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x2000FFFF;
define symbol __ICFEDIT_region_IRAM3_start__ = 0x20010000;
define symbol __ICFEDIT_region_IRAM3_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_IRAM4_start__ = 0x20020000;
define symbol __ICFEDIT_region_IRAM4_end__ = 0x20026FFF;
define symbol __ICFEDIT_region_IRAM5_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM5_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]
| mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__]
| mem:[from __ICFEDIT_region_IRAM4_start__ to __ICFEDIT_region_IRAM4_end__]
| mem:[from __ICFEDIT_region_IRAM5_start__ to __ICFEDIT_region_IRAM5_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x1FFF8000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFF8000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFCFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFFD000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x2000FFFF;
define symbol __ICFEDIT_region_IRAM3_start__ = 0x20010000;
define symbol __ICFEDIT_region_IRAM3_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_IRAM4_start__ = 0x20020000;
define symbol __ICFEDIT_region_IRAM4_end__ = 0x20026FFF;
define symbol __ICFEDIT_region_IRAM5_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM5_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x100;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x100;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]
| mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__]
| mem:[from __ICFEDIT_region_IRAM4_start__ to __ICFEDIT_region_IRAM4_end__]
| mem:[from __ICFEDIT_region_IRAM5_start__ to __ICFEDIT_region_IRAM5_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\HwCodeCnt.ewp</path>
</project>
<batchBuild/>
</workspace>

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<?xml version="1.0" encoding="iso-8859-1"?>
<flash_device>
<exe>$PROJ_DIR$\..\..\..\..\mcu\EWARM\config\flashloader\FlashHC32F460_otp.out</exe>
<page>4</page>
<block>64 0x10</block>
<flash_base>0x03000C00</flash_base>
<macro>$PROJ_DIR$\..\..\..\..\mcu\EWARM\config\flashloader\FlashHC32F460_otp.mac</macro>
<aggregate>0</aggregate>
</flash_device>

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<?xml version="1.0" encoding="iso-8859-1"?>
<flash_device>
<exe>$PROJ_DIR$\..\..\..\..\mcu\EWARM\config\flashloader\FlashHC32F460.out</exe>
<page>4</page>
<block>32 0x2000</block>
<flash_base>0x00000000</flash_base>
<macro>$PROJ_DIR$\..\..\..\..\mcu\EWARM\config\flashloader\FlashHC32F460.mac</macro>
<aggregate>0</aggregate>
</flash_device>

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<?xml version="1.0" encoding="iso-8859-1"?>
<flash_device>
<exe>$PROJ_DIR$\..\..\..\..\mcu\EWARM\config\flashloader\FlashHC32F460.out</exe>
<page>4</page>
<block>64 0x2000</block>
<flash_base>0x00000000</flash_base>
<macro>$PROJ_DIR$\..\..\..\..\mcu\EWARM\config\flashloader\FlashHC32F460.mac</macro>
<aggregate>0</aggregate>
</flash_device>

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<?xml version="1.0" encoding="iso-8859-1"?>
<flash_board>
<pass>
<loader>$PROJ_DIR$\flashloader\FlashHC32F460xC.flash</loader>
<range>CODE 0x0 0x3FFFF</range>
</pass>
<pass>
<loader>$PROJ_DIR$\flashloader\FlashHC32F460_otp.flash</loader>
<range>CODE 0x03000C00 0x03000FFB</range>
</pass>
</flash_board>

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<?xml version="1.0" encoding="iso-8859-1"?>
<flash_board>
<pass>
<loader>$PROJ_DIR$\flashloader\FlashHC32F460xE.flash</loader>
<range>CODE 0x0 0x7FFFF</range>
</pass>
<pass>
<loader>$PROJ_DIR$\flashloader\FlashHC32F460_otp.flash</loader>
<range>CODE 0x03000C00 0x03000FFB</range>
</pass>
</flash_board>

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[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="Cortex-M4"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

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[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="Cortex-M4"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

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<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1673155477331400536" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1955898745" name="Release">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1624988756903161501" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
</project>

View File

@@ -0,0 +1,71 @@
<?xml version='1.0' encoding='UTF-8' standalone='no'?>
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.pyocd.launchConfigurationType">
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;peripherals/&gt;&#13;&#10;"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doContinue" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doDebugInRam" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doFirstReset" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doGdbServerAllocateConsole" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doGdbServerAllocateSemihostingConsole" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doSecondReset" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doStartGdbServer" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.enableSemihosting" value="true"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.firstResetType" value="init"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherOptions" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerBoardId" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerBoardName" value=""/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerBusSpeed" value="1000000"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerConnectionAddress" value=""/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerEnableSemihosting" value="true"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerExecutable" value="${pyocd_path}/${pyocd_executable}"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerFlashFastVerify" value="false"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerFlashMode" value="0"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerGdbPortNumber" value="3333"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerHaltAtHardFault" value="true"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerLog" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerOther" value=""/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerOverrideTarget" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerStepIntoInterrutps" value="false"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerTargetName" value="hc32f460xe"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerTelnetPortNumber" value="4444"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerUseGdbSyscalls" value="false"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherRunCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.secondResetType" value="halt"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}\..\..\..\..\mcu\GCC\SVD\HDSC_HC32F46X.svd"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU PyOCD"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug\HwCodeCnt.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="HwCodeCnt"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.439039181"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/HwCodeCnt"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>

View File

@@ -0,0 +1,6 @@
<?xml version='1.0' encoding='UTF-8' standalone='no'?>
<launchConfiguration type="org.eclipse.ui.externaltools.ProgramLaunchConfigurationType">
<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LOCATION" value="\pyocd.exe"/>
<stringAttribute key="org.eclipse.ui.externaltools.ATTR_TOOL_ARGUMENTS" value="flash -t hc32f46x HwCodeCnt.hex"/>
<stringAttribute key="org.eclipse.ui.externaltools.ATTR_WORKING_DIRECTORY" value="${project_loc}\Debug"/>
</launchConfiguration>

View File

@@ -0,0 +1,234 @@
/*
;*******************************************************************************
; Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
;
; This software is owned and published by:
; Huada Semiconductor Co.,Ltd ("HDSC").
;
; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
;
; This software contains source code for use with HDSC
; components. This software is licensed by HDSC to be adapted only
; for use in systems utilizing HDSC components. HDSC shall not be
; responsible for misuse or illegal use of this software for devices not
; supported herein. HDSC is providing this software "AS IS" and will
; not be responsible for issues arising from incorrect user implementation
; of the software.
;
; Disclaimer:
; HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
; REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
; WARRANTY OF NONINFRINGEMENT.
; HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
; SAVINGS OR PROFITS,
; EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
; FROM, THE SOFTWARE.
;
; This software may be replicated in part or whole for the licensed use,
; with the restriction that this Disclaimer and Copyright notice must be
; included with each copy of this software, whether used in part or whole,
; at all times.
;/
*/
/*****************************************************************************/
/* File hc32f46xc_flash.ld */
/* Abstract Linker script for HC32F46x Device with */
/* 256KByte FLASH, 192KByte RAM */
/* Version V1.0 */
/* Date 2019-03-13 */
/*****************************************************************************/
/* Use contiguous memory regions for simple. */
MEMORY
{
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 256K
OTP (rx): ORIGIN = 0x03000C00, LENGTH = 1020
RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K
RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
}
ENTRY(Reset_Handler)
SECTIONS
{
.vectors :
{
. = ALIGN(4);
KEEP(*(.vectors))
. = ALIGN(4);
} >FLASH
.icg_sec 0x00000400 :
{
KEEP(*(.icg_sec))
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP(*(.init))
KEEP(*(.fini))
. = ALIGN(4);
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >FLASH
__exidx_end = .;
.preinit_array :
{
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH
.init_array :
{
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH
.fini_array :
{
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} >FLASH
__etext = ALIGN(4);
.otp_sec :
{
KEEP(*(.otp_sec))
} >OTP
.otp_lock_sec 0x03000FC0 :
{
KEEP(*(.otp_lock_sec))
} >OTP
.data : AT (__etext)
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
. = ALIGN(4);
*(.ramfunc)
*(.ramfunc*)
. = ALIGN(4);
__data_end__ = .;
} >RAM
__etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
.ret_ram_data : AT (__etext_ret_ram)
{
. = ALIGN(4);
__data_start_ret_ram__ = .;
*(.ret_ram_data)
*(.ret_ram_data*)
. = ALIGN(4);
__data_end_ret_ram__ = .;
} >RET_RAM
.bss :
{
. = ALIGN(4);
_sbss = .;
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
__bss_end__ = _ebss;
} >RAM
.ret_ram_bss :
{
. = ALIGN(4);
__bss_start_ret_ram__ = .;
*(.ret_ram_bss)
*(.ret_ram_bss*)
. = ALIGN(4);
__bss_end_ret_ram__ = .;
} >RET_RAM
.heap_stack (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
*(.heap*)
. = ALIGN(8);
__HeapLimit = .;
__StackLimit = .;
*(.stack*)
. = ALIGN(8);
__StackTop = .;
} >RAM
/DISCARD/ :
{
libc.a (*)
libm.a (*)
libgcc.a (*)
}
.ARM.attributes 0 : { *(.ARM.attributes) }
PROVIDE(_stack = __StackTop);
PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
}

View File

@@ -0,0 +1,234 @@
/*
;*******************************************************************************
; Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
;
; This software is owned and published by:
; Huada Semiconductor Co.,Ltd ("HDSC").
;
; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
;
; This software contains source code for use with HDSC
; components. This software is licensed by HDSC to be adapted only
; for use in systems utilizing HDSC components. HDSC shall not be
; responsible for misuse or illegal use of this software for devices not
; supported herein. HDSC is providing this software "AS IS" and will
; not be responsible for issues arising from incorrect user implementation
; of the software.
;
; Disclaimer:
; HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
; REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
; WARRANTY OF NONINFRINGEMENT.
; HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
; SAVINGS OR PROFITS,
; EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
; FROM, THE SOFTWARE.
;
; This software may be replicated in part or whole for the licensed use,
; with the restriction that this Disclaimer and Copyright notice must be
; included with each copy of this software, whether used in part or whole,
; at all times.
;/
*/
/*****************************************************************************/
/* File hc32f46x_flash.ld */
/* Abstract Linker script for HC32F46x Device with */
/* 512KByte FLASH, 192KByte RAM */
/* Version V1.0 */
/* Date 2019-03-13 */
/*****************************************************************************/
/* Use contiguous memory regions for simple. */
MEMORY
{
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 512K
OTP (rx): ORIGIN = 0x03000C00, LENGTH = 1020
RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 188K
RET_RAM (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
}
ENTRY(Reset_Handler)
SECTIONS
{
.vectors :
{
. = ALIGN(4);
KEEP(*(.vectors))
. = ALIGN(4);
} >FLASH
.icg_sec 0x00000400 :
{
KEEP(*(.icg_sec))
} >FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text*)
*(.glue_7)
*(.glue_7t)
*(.eh_frame)
KEEP(*(.init))
KEEP(*(.fini))
. = ALIGN(4);
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >FLASH
__exidx_end = .;
.preinit_array :
{
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH
.init_array :
{
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH
.fini_array :
{
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} >FLASH
__etext = ALIGN(4);
.otp_sec :
{
KEEP(*(.otp_sec))
} >OTP
.otp_lock_sec 0x03000FC0 :
{
KEEP(*(.otp_lock_sec))
} >OTP
.data : AT (__etext)
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
. = ALIGN(4);
*(.ramfunc)
*(.ramfunc*)
. = ALIGN(4);
__data_end__ = .;
} >RAM
__etext_ret_ram = __etext + ALIGN (SIZEOF(.data), 4);
.ret_ram_data : AT (__etext_ret_ram)
{
. = ALIGN(4);
__data_start_ret_ram__ = .;
*(.ret_ram_data)
*(.ret_ram_data*)
. = ALIGN(4);
__data_end_ret_ram__ = .;
} >RET_RAM
.bss :
{
. = ALIGN(4);
_sbss = .;
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
__bss_end__ = _ebss;
} >RAM
.ret_ram_bss :
{
. = ALIGN(4);
__bss_start_ret_ram__ = .;
*(.ret_ram_bss)
*(.ret_ram_bss*)
. = ALIGN(4);
__bss_end_ret_ram__ = .;
} >RET_RAM
.heap_stack (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
*(.heap*)
. = ALIGN(8);
__HeapLimit = .;
__StackLimit = .;
*(.stack*)
. = ALIGN(8);
__StackTop = .;
} >RAM
/DISCARD/ :
{
libc.a (*)
libm.a (*)
libgcc.a (*)
}
.ARM.attributes 0 : { *(.ARM.attributes) }
PROVIDE(_stack = __StackTop);
PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
}

View File

@@ -0,0 +1,572 @@
/*
;*******************************************************************************
; Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
;
; This software is owned and published by:
; Huada Semiconductor Co.,Ltd ("HDSC").
;
; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
;
; This software contains source code for use with HDSC
; components. This software is licensed by HDSC to be adapted only
; for use in systems utilizing HDSC components. HDSC shall not be
; responsible for misuse or illegal use of this software for devices not
; supported herein. HDSC is providing this software "AS IS" and will
; not be responsible for issues arising from incorrect user implementation
; of the software.
;
; Disclaimer:
; HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
; REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
; WARRANTY OF NONINFRINGEMENT.
; HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
; SAVINGS OR PROFITS,
; EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
; FROM, THE SOFTWARE.
;
; This software may be replicated in part or whole for the licensed use,
; with the restriction that this Disclaimer and Copyright notice must be
; included with each copy of this software, whether used in part or whole,
; at all times.
;/
*/
/*****************************************************************************/
/* Startup for GCC */
/* Version V1.0 */
/* Date 2019-03-13 */
/* Target-mcu HC32F46x */
/*****************************************************************************/
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv7e-m
.cpu cortex-m4
.fpu softvfp
.thumb
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00000400
.section .stack
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00000C00
.if Heap_Size != 0 /* Heap is provided */
.section .heap
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.endif
/*
;<h> Interrupt vector table start.
*/
.section .vectors, "a", %progbits
.align 2
.type __Vectors, %object
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* -14 NMI Handler */
.long HardFault_Handler /* -13 Hard Fault Handler */
.long MemManage_Handler /* -12 MPU Fault Handler */
.long BusFault_Handler /* -11 Bus Fault Handler */
.long UsageFault_Handler /* -10 Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* -5 SVCall Handler */
.long DebugMon_Handler /* -4 Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* -2 PendSV Handler */
.long SysTick_Handler /* -1 SysTick Handler */
/* Interrupts */
.long IRQ000_Handler
.long IRQ001_Handler
.long IRQ002_Handler
.long IRQ003_Handler
.long IRQ004_Handler
.long IRQ005_Handler
.long IRQ006_Handler
.long IRQ007_Handler
.long IRQ008_Handler
.long IRQ009_Handler
.long IRQ010_Handler
.long IRQ011_Handler
.long IRQ012_Handler
.long IRQ013_Handler
.long IRQ014_Handler
.long IRQ015_Handler
.long IRQ016_Handler
.long IRQ017_Handler
.long IRQ018_Handler
.long IRQ019_Handler
.long IRQ020_Handler
.long IRQ021_Handler
.long IRQ022_Handler
.long IRQ023_Handler
.long IRQ024_Handler
.long IRQ025_Handler
.long IRQ026_Handler
.long IRQ027_Handler
.long IRQ028_Handler
.long IRQ029_Handler
.long IRQ030_Handler
.long IRQ031_Handler
.long IRQ032_Handler
.long IRQ033_Handler
.long IRQ034_Handler
.long IRQ035_Handler
.long IRQ036_Handler
.long IRQ037_Handler
.long IRQ038_Handler
.long IRQ039_Handler
.long IRQ040_Handler
.long IRQ041_Handler
.long IRQ042_Handler
.long IRQ043_Handler
.long IRQ044_Handler
.long IRQ045_Handler
.long IRQ046_Handler
.long IRQ047_Handler
.long IRQ048_Handler
.long IRQ049_Handler
.long IRQ050_Handler
.long IRQ051_Handler
.long IRQ052_Handler
.long IRQ053_Handler
.long IRQ054_Handler
.long IRQ055_Handler
.long IRQ056_Handler
.long IRQ057_Handler
.long IRQ058_Handler
.long IRQ059_Handler
.long IRQ060_Handler
.long IRQ061_Handler
.long IRQ062_Handler
.long IRQ063_Handler
.long IRQ064_Handler
.long IRQ065_Handler
.long IRQ066_Handler
.long IRQ067_Handler
.long IRQ068_Handler
.long IRQ069_Handler
.long IRQ070_Handler
.long IRQ071_Handler
.long IRQ072_Handler
.long IRQ073_Handler
.long IRQ074_Handler
.long IRQ075_Handler
.long IRQ076_Handler
.long IRQ077_Handler
.long IRQ078_Handler
.long IRQ079_Handler
.long IRQ080_Handler
.long IRQ081_Handler
.long IRQ082_Handler
.long IRQ083_Handler
.long IRQ084_Handler
.long IRQ085_Handler
.long IRQ086_Handler
.long IRQ087_Handler
.long IRQ088_Handler
.long IRQ089_Handler
.long IRQ090_Handler
.long IRQ091_Handler
.long IRQ092_Handler
.long IRQ093_Handler
.long IRQ094_Handler
.long IRQ095_Handler
.long IRQ096_Handler
.long IRQ097_Handler
.long IRQ098_Handler
.long IRQ099_Handler
.long IRQ100_Handler
.long IRQ101_Handler
.long IRQ102_Handler
.long IRQ103_Handler
.long IRQ104_Handler
.long IRQ105_Handler
.long IRQ106_Handler
.long IRQ107_Handler
.long IRQ108_Handler
.long IRQ109_Handler
.long IRQ110_Handler
.long IRQ111_Handler
.long IRQ112_Handler
.long IRQ113_Handler
.long IRQ114_Handler
.long IRQ115_Handler
.long IRQ116_Handler
.long IRQ117_Handler
.long IRQ118_Handler
.long IRQ119_Handler
.long IRQ120_Handler
.long IRQ121_Handler
.long IRQ122_Handler
.long IRQ123_Handler
.long IRQ124_Handler
.long IRQ125_Handler
.long IRQ126_Handler
.long IRQ127_Handler
.long IRQ128_Handler
.long IRQ129_Handler
.long IRQ130_Handler
.long IRQ131_Handler
.long IRQ132_Handler
.long IRQ133_Handler
.long IRQ134_Handler
.long IRQ135_Handler
.long IRQ136_Handler
.long IRQ137_Handler
.long IRQ138_Handler
.long IRQ139_Handler
.long IRQ140_Handler
.long IRQ141_Handler
.long IRQ142_Handler
.long IRQ143_Handler
.space (80 * 4) /* Interrupts 144 .. 224 are left out */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.size __Vectors, . - __Vectors
/*
;<h> Interrupt vector table end.
*/
/*
;<h> Reset handler start.
*/
.section .text.Reset_Handler
.align 2
.weak Reset_Handler
.type Reset_Handler, %function
.globl Reset_Handler
Reset_Handler:
/* Set stack top pointer. */
ldr sp, =__StackTop
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
/* Copy data from read only memory to RAM. */
CopyData:
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
CopyLoop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt CopyLoop
CopyData1:
ldr r1, =__etext_ret_ram
ldr r2, =__data_start_ret_ram__
ldr r3, =__data_end_ret_ram__
CopyLoop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt CopyLoop1
/* This part of work usually is done in C library startup code.
* Otherwise, define this macro to enable it in this startup.
*
* There are two schemes too.
* One can clear multiple BSS sections. Another can only clear one section.
* The former is more size expensive than the latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
/* Clear BSS section. */
ClearBss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
ClearLoop:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt ClearLoop
ClearBss1:
ldr r1, =__bss_start_ret_ram__
ldr r2, =__bss_end_ret_ram__
movs r0, 0
ClearLoop1:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt ClearLoop1
SetSRAM3Wait:
ldr r0, =0x40050804
mov r1, #0x77
str r1, [r0]
ldr r0, =0x4005080C
mov r1, #0x77
str r1, [r0]
ldr r0, =0x40050800
mov r1, #0x1100
str r1, [r0]
ldr r0, =0x40050804
mov r1, #0x76
str r1, [r0]
ldr r0, =0x4005080C
mov r1, #0x76
str r1, [r0]
/* Call the clock system initialization function. */
bl SystemInit
/* Call the application's entry point. */
bl main
bx lr
.size Reset_Handler, . - Reset_Handler
/*
;<h> Reset handler end.
*/
/*
;<h> Default handler start.
*/
.section .text.Default_Handler, "ax", %progbits
.align 2
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/*
;<h> Default handler end.
*/
/* Macro to define default exception/interrupt handlers.
* Default handler are weak symbols with an endless loop.
* They can be overwritten by real handlers.
*/
.macro Set_Default_Handler Handler_Name
.weak \Handler_Name
.set \Handler_Name, Default_Handler
.endm
/* Default exception/interrupt handler */
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler IRQ000_Handler
Set_Default_Handler IRQ001_Handler
Set_Default_Handler IRQ002_Handler
Set_Default_Handler IRQ003_Handler
Set_Default_Handler IRQ004_Handler
Set_Default_Handler IRQ005_Handler
Set_Default_Handler IRQ006_Handler
Set_Default_Handler IRQ007_Handler
Set_Default_Handler IRQ008_Handler
Set_Default_Handler IRQ009_Handler
Set_Default_Handler IRQ010_Handler
Set_Default_Handler IRQ011_Handler
Set_Default_Handler IRQ012_Handler
Set_Default_Handler IRQ013_Handler
Set_Default_Handler IRQ014_Handler
Set_Default_Handler IRQ015_Handler
Set_Default_Handler IRQ016_Handler
Set_Default_Handler IRQ017_Handler
Set_Default_Handler IRQ018_Handler
Set_Default_Handler IRQ019_Handler
Set_Default_Handler IRQ020_Handler
Set_Default_Handler IRQ021_Handler
Set_Default_Handler IRQ022_Handler
Set_Default_Handler IRQ023_Handler
Set_Default_Handler IRQ024_Handler
Set_Default_Handler IRQ025_Handler
Set_Default_Handler IRQ026_Handler
Set_Default_Handler IRQ027_Handler
Set_Default_Handler IRQ028_Handler
Set_Default_Handler IRQ029_Handler
Set_Default_Handler IRQ030_Handler
Set_Default_Handler IRQ031_Handler
Set_Default_Handler IRQ032_Handler
Set_Default_Handler IRQ033_Handler
Set_Default_Handler IRQ034_Handler
Set_Default_Handler IRQ035_Handler
Set_Default_Handler IRQ036_Handler
Set_Default_Handler IRQ037_Handler
Set_Default_Handler IRQ038_Handler
Set_Default_Handler IRQ039_Handler
Set_Default_Handler IRQ040_Handler
Set_Default_Handler IRQ041_Handler
Set_Default_Handler IRQ042_Handler
Set_Default_Handler IRQ043_Handler
Set_Default_Handler IRQ044_Handler
Set_Default_Handler IRQ045_Handler
Set_Default_Handler IRQ046_Handler
Set_Default_Handler IRQ047_Handler
Set_Default_Handler IRQ048_Handler
Set_Default_Handler IRQ049_Handler
Set_Default_Handler IRQ050_Handler
Set_Default_Handler IRQ051_Handler
Set_Default_Handler IRQ052_Handler
Set_Default_Handler IRQ053_Handler
Set_Default_Handler IRQ054_Handler
Set_Default_Handler IRQ055_Handler
Set_Default_Handler IRQ056_Handler
Set_Default_Handler IRQ057_Handler
Set_Default_Handler IRQ058_Handler
Set_Default_Handler IRQ059_Handler
Set_Default_Handler IRQ060_Handler
Set_Default_Handler IRQ061_Handler
Set_Default_Handler IRQ062_Handler
Set_Default_Handler IRQ063_Handler
Set_Default_Handler IRQ064_Handler
Set_Default_Handler IRQ065_Handler
Set_Default_Handler IRQ066_Handler
Set_Default_Handler IRQ067_Handler
Set_Default_Handler IRQ068_Handler
Set_Default_Handler IRQ069_Handler
Set_Default_Handler IRQ070_Handler
Set_Default_Handler IRQ071_Handler
Set_Default_Handler IRQ072_Handler
Set_Default_Handler IRQ073_Handler
Set_Default_Handler IRQ074_Handler
Set_Default_Handler IRQ075_Handler
Set_Default_Handler IRQ076_Handler
Set_Default_Handler IRQ077_Handler
Set_Default_Handler IRQ078_Handler
Set_Default_Handler IRQ079_Handler
Set_Default_Handler IRQ080_Handler
Set_Default_Handler IRQ081_Handler
Set_Default_Handler IRQ082_Handler
Set_Default_Handler IRQ083_Handler
Set_Default_Handler IRQ084_Handler
Set_Default_Handler IRQ085_Handler
Set_Default_Handler IRQ086_Handler
Set_Default_Handler IRQ087_Handler
Set_Default_Handler IRQ088_Handler
Set_Default_Handler IRQ089_Handler
Set_Default_Handler IRQ090_Handler
Set_Default_Handler IRQ091_Handler
Set_Default_Handler IRQ092_Handler
Set_Default_Handler IRQ093_Handler
Set_Default_Handler IRQ094_Handler
Set_Default_Handler IRQ095_Handler
Set_Default_Handler IRQ096_Handler
Set_Default_Handler IRQ097_Handler
Set_Default_Handler IRQ098_Handler
Set_Default_Handler IRQ099_Handler
Set_Default_Handler IRQ100_Handler
Set_Default_Handler IRQ101_Handler
Set_Default_Handler IRQ102_Handler
Set_Default_Handler IRQ103_Handler
Set_Default_Handler IRQ104_Handler
Set_Default_Handler IRQ105_Handler
Set_Default_Handler IRQ106_Handler
Set_Default_Handler IRQ107_Handler
Set_Default_Handler IRQ108_Handler
Set_Default_Handler IRQ109_Handler
Set_Default_Handler IRQ110_Handler
Set_Default_Handler IRQ111_Handler
Set_Default_Handler IRQ112_Handler
Set_Default_Handler IRQ113_Handler
Set_Default_Handler IRQ114_Handler
Set_Default_Handler IRQ115_Handler
Set_Default_Handler IRQ116_Handler
Set_Default_Handler IRQ117_Handler
Set_Default_Handler IRQ118_Handler
Set_Default_Handler IRQ119_Handler
Set_Default_Handler IRQ120_Handler
Set_Default_Handler IRQ121_Handler
Set_Default_Handler IRQ122_Handler
Set_Default_Handler IRQ123_Handler
Set_Default_Handler IRQ124_Handler
Set_Default_Handler IRQ125_Handler
Set_Default_Handler IRQ126_Handler
Set_Default_Handler IRQ127_Handler
Set_Default_Handler IRQ128_Handler
Set_Default_Handler IRQ129_Handler
Set_Default_Handler IRQ130_Handler
Set_Default_Handler IRQ131_Handler
Set_Default_Handler IRQ132_Handler
Set_Default_Handler IRQ133_Handler
Set_Default_Handler IRQ134_Handler
Set_Default_Handler IRQ135_Handler
Set_Default_Handler IRQ136_Handler
Set_Default_Handler IRQ137_Handler
Set_Default_Handler IRQ138_Handler
Set_Default_Handler IRQ139_Handler
Set_Default_Handler IRQ140_Handler
Set_Default_Handler IRQ141_Handler
Set_Default_Handler IRQ142_Handler
Set_Default_Handler IRQ143_Handler
.end

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@@ -0,0 +1,982 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>HwCodeCnt_Debug</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
<TargetOption>
<TargetCommonOption>
<Device>HC32F460PETB</Device>
<Vendor>HDSC</Vendor>
<PackID>HDSC.HC32F46x.1.0.0</PackID>
<PackURL>https://raw.githubusercontent.com/hdscmcu/pack/master/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IROM2(0x03000C00,0x3FC) IRAM(0x1FFF8000,0x2F000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>JL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F46x_512K -FS00 -FL080000 -FP0($$Device:HC32F460PETB$FlashARM\HC32F46x_512K.FLM) -FF1HC32F46x_otp -FS13000C00 -FL13FC -FP1($$Device:HC32F460PETB$FlashARM\HC32F46x_otp.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:HC32F460PETB$Device\Include\hc32f460p.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>./../../../..\mcu\MDK\hdsc_hc32f46x.SFR</SFDFile>
<bCustSvd>1</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\output\debug\</OutputDirectory>
<OutputName>HwCodeCnt</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\output\debug\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
<RestoreSysVw>1</RestoreSysVw>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>0</RestoreTracepoints>
<RestoreSysVw>1</RestoreSysVw>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>6</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>Segger\JL2CM3.dll</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>1</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x1fff8000</StartAddress>
<Size>0x2f000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x03000c00</StartAddress>
<Size>0x3FC</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x1fff8000</StartAddress>
<Size>0x2F000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x200F0000</StartAddress>
<Size>0x1000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--diag_suppress=186,66</MiscControls>
<Define>__DEBUG,HC32F46x,USE_DEVICE_DRIVER_LIB</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\mcu\common;..\source;..\..\..\..\driver\inc;<custom>{PROJ_MIDWARE_INC}</custom></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x1FFF8000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>HwCodeCnt.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>--keep=*Handler</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>common</GroupName>
<Files>
<File>
<FileName>startup_hc32f46x.s</FileName>
<FileType>2</FileType>
<FilePath>.\startup_hc32f46x.s</FilePath>
</File>
<File>
<FileName>system_hc32f46x.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\mcu\common\system_hc32f46x.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>source</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>..\source\main.c</FilePath>
</File>
<custom>{PROJ_USB_SRC}</custom>
</Files>
</Group>
<Group>
<GroupName>driver</GroupName>
<Files>
<!--
<File>
<FileName>gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\driver\src\gpio.c</FilePath>
</File>
-->
<File>
<FileName>hc32f46x_icg.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_icg.c</FilePath></File>
<File>
<FileName>hc32f46x_utility.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_utility.c</FilePath></File>
<File>
<FileName>hc32f46x_clk.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_clk.c</FilePath></File>
<File>
<FileName>hc32f46x_efm.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_efm.c</FilePath></File>
<File>
<FileName>hc32f46x_gpio.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_gpio.c</FilePath></File>
<File>
<FileName>hc32f46x_interrupts.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_interrupts.c</FilePath></File>
<File>
<FileName>hc32f46x_pwc.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_pwc.c</FilePath></File>
<File>
<FileName>hc32f46x_timer6.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_timer6.c</FilePath></File>
</Files>
</Group>
<custom>{PROJ_MIDWARE_SRC}</custom>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
</Groups>
</Target>
<Target>
<TargetName>HwCodeCnt_Release</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
<TargetOption>
<TargetCommonOption>
<Device>HC32F460PETB</Device>
<Vendor>HDSC</Vendor>
<PackID>HDSC.HC32F46x.1.0.0</PackID>
<PackURL>https://raw.githubusercontent.com/hdscmcu/pack/master/</PackURL>
<Cpu>IROM(0x00000000,0x80000) IROM2(0x03000C00,0x3FC) IRAM2(0x200F0000,0x1000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>JL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN2 -FF0HC32F46x_512K -FS00 -FL080000 -FP0($$Device:HC32F460PETB$Flash\HC32F46x_512K.FLM) -FF1HC32F46x_otp -FS13000C00 -FL13FC -FP1($$Device:HC32F460PETB$Flash\HC32F46x_otp.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:HC32F460PETB$Device\Include\hc32f460p.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>./../../../..\mcu\MDK\hdsc_hc32f46x.SFR</SFDFile>
<bCustSvd>1</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\output\release\</OutputDirectory>
<OutputName>HwCodeCnt</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>0</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\output\release\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
<RestoreSysVw>1</RestoreSysVw>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>0</RestoreTracepoints>
<RestoreSysVw>1</RestoreSysVw>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>6</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>Segger\JL2CM3.dll</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>0</AdsALst>
<AdsACrf>0</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>0</AdsLcgr>
<AdsLsym>0</AdsLsym>
<AdsLszi>0</AdsLszi>
<AdsLtoi>0</AdsLtoi>
<AdsLsun>0</AdsLsun>
<AdsLven>0</AdsLven>
<AdsLsxf>0</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>1</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x1fff8000</StartAddress>
<Size>0x2F000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x1fff8000</StartAddress>
<Size>0x2F000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x200F0000</StartAddress>
<Size>0x1000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>4</Optim>
<oTime>1</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<useXO>0</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<VariousControls>
<MiscControls>--diag_suppress=186,66</MiscControls>
<Define>HC32F46x,USE_DEVICE_DRIVER_LIB</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\mcu\common;..\source;..\..\..\..\driver\inc;<custom>{PROJ_MIDWARE_INC}</custom></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x1FFF8000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>HwCodeCnt.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>--keep=*Handler</Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>common</GroupName>
<Files>
<File>
<FileName>startup_hc32f46x.s</FileName>
<FileType>2</FileType>
<FilePath>.\startup_hc32f46x.s</FilePath>
</File>
<File>
<FileName>system_hc32f46x.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\mcu\common\system_hc32f46x.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>source</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>..\source\main.c</FilePath>
</File>
<custom>{PROJ_USB_SRC}</custom>
</Files>
</Group>
<Group>
<GroupName>driver</GroupName>
<Files>
<!--
<File>
<FileName>gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\driver\src\gpio.c</FilePath>
</File>
-->
<File>
<FileName>hc32f46x_icg.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_icg.c</FilePath></File>
<File>
<FileName>hc32f46x_utility.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_utility.c</FilePath></File>
<File>
<FileName>hc32f46x_clk.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_clk.c</FilePath></File>
<File>
<FileName>hc32f46x_efm.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_efm.c</FilePath></File>
<File>
<FileName>hc32f46x_gpio.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_gpio.c</FilePath></File>
<File>
<FileName>hc32f46x_interrupts.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_interrupts.c</FilePath></File>
<File>
<FileName>hc32f46x_pwc.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_pwc.c</FilePath></File>
<File>
<FileName>hc32f46x_timer6.c</FileName>
<FileType>1</FileType><FilePath>..\..\..\..\driver\src\hc32f46x_timer6.c</FilePath></File>
</Files>
</Group>
<custom>{PROJ_MIDWARE_SRC}</custom>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.1.0" condition="CMSIS Core">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
<targetInfos>
<targetInfo name="HwCodeCnt_Debug"/>
<targetInfo name="HwCodeCnt_Release"/>
</targetInfos>
</component>
</components>
</RTE>
</Project>

View File

@@ -0,0 +1,35 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="Cortex-M4"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

View File

@@ -0,0 +1,657 @@
;/******************************************************************************
;* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
;*
;* This software is owned and published by:
;* Huada Semiconductor Co.,Ltd ("HDSC").
;*
;* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
;* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
;*
;* This software contains source code for use with HDSC
;* components. This software is licensed by HDSC to be adapted only
;* for use in systems utilizing HDSC components. HDSC shall not be
;* responsible for misuse or illegal use of this software for devices not
;* supported herein. HDSC is providing this software "AS IS" and will
;* not be responsible for issues arising from incorrect user implementation
;* of the software.
;*
;* Disclaimer:
;* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
;* REGARDING THE SOFTWARE (INCLUDING ANY ACCOMPANYING WRITTEN MATERIALS),
;* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
;* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
;* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
;* WARRANTY OF NONINFRINGEMENT.
;* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
;* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
;* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
;* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
;* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
;* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
;* SAVINGS OR PROFITS,
;* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
;* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
;* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
;* FROM, THE SOFTWARE.
;*
;* This software may be replicated in part or whole for the licensed use,
;* with the restriction that this Disclaimer and Copyright notice must be
;* included with each copy of this software, whether used in part or whole,
;* at all times.
;*/
;/*****************************************************************************/
;/*****************************************************************************/
;/* Startup for ARM */
;/* Version V1.0 */
;/* Date 2018-10-13 */
;/* Target-mcu HC32F46x */
;/*****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Peripheral Interrupts
DCD IRQ000_Handler ; IRQ000_Handler
DCD IRQ001_Handler ; IRQ001_Handler
DCD IRQ002_Handler ; IRQ002_Handler
DCD IRQ003_Handler ; IRQ003_Handler
DCD IRQ004_Handler ; IRQ004_Handler
DCD IRQ005_Handler ; IRQ005_Handler
DCD IRQ006_Handler ; IRQ006_Handler
DCD IRQ007_Handler ; IRQ007_Handler
DCD IRQ008_Handler ; IRQ008_Handler
DCD IRQ009_Handler ; IRQ009_Handler
DCD IRQ010_Handler ; IRQ010_Handler
DCD IRQ011_Handler ; IRQ011_Handler
DCD IRQ012_Handler ; IRQ012_Handler
DCD IRQ013_Handler ; IRQ013_Handler
DCD IRQ014_Handler ; IRQ014_Handler
DCD IRQ015_Handler ; IRQ015_Handler
DCD IRQ016_Handler ; IRQ016_Handler
DCD IRQ017_Handler ; IRQ017_Handler
DCD IRQ018_Handler ; IRQ018_Handler
DCD IRQ019_Handler ; IRQ019_Handler
DCD IRQ020_Handler ; IRQ020_Handler
DCD IRQ021_Handler ; IRQ021_Handler
DCD IRQ022_Handler ; IRQ022_Handler
DCD IRQ023_Handler ; IRQ023_Handler
DCD IRQ024_Handler ; IRQ024_Handler
DCD IRQ025_Handler ; IRQ025_Handler
DCD IRQ026_Handler ; IRQ026_Handler
DCD IRQ027_Handler ; IRQ027_Handler
DCD IRQ028_Handler ; IRQ028_Handler
DCD IRQ029_Handler ; IRQ029_Handler
DCD IRQ030_Handler ; IRQ030_Handler
DCD IRQ031_Handler ; IRQ031_Handler
DCD IRQ032_Handler ; IRQ032_Handler
DCD IRQ033_Handler ; IRQ033_Handler
DCD IRQ034_Handler ; IRQ034_Handler
DCD IRQ035_Handler ; IRQ035_Handler
DCD IRQ036_Handler ; IRQ036_Handler
DCD IRQ037_Handler ; IRQ037_Handler
DCD IRQ038_Handler ; IRQ038_Handler
DCD IRQ039_Handler ; IRQ039_Handler
DCD IRQ040_Handler ; IRQ040_Handler
DCD IRQ041_Handler ; IRQ041_Handler
DCD IRQ042_Handler ; IRQ042_Handler
DCD IRQ043_Handler ; IRQ043_Handler
DCD IRQ044_Handler ; IRQ044_Handler
DCD IRQ045_Handler ; IRQ045_Handler
DCD IRQ046_Handler ; IRQ046_Handler
DCD IRQ047_Handler ; IRQ047_Handler
DCD IRQ048_Handler ; IRQ048_Handler
DCD IRQ049_Handler ; IRQ049_Handler
DCD IRQ050_Handler ; IRQ050_Handler
DCD IRQ051_Handler ; IRQ051_Handler
DCD IRQ052_Handler ; IRQ052_Handler
DCD IRQ053_Handler ; IRQ053_Handler
DCD IRQ054_Handler ; IRQ054_Handler
DCD IRQ055_Handler ; IRQ055_Handler
DCD IRQ056_Handler ; IRQ056_Handler
DCD IRQ057_Handler ; IRQ057_Handler
DCD IRQ058_Handler ; IRQ058_Handler
DCD IRQ059_Handler ; IRQ059_Handler
DCD IRQ060_Handler ; IRQ060_Handler
DCD IRQ061_Handler ; IRQ061_Handler
DCD IRQ062_Handler ; IRQ062_Handler
DCD IRQ063_Handler ; IRQ063_Handler
DCD IRQ064_Handler ; IRQ064_Handler
DCD IRQ065_Handler ; IRQ065_Handler
DCD IRQ066_Handler ; IRQ066_Handler
DCD IRQ067_Handler ; IRQ067_Handler
DCD IRQ068_Handler ; IRQ068_Handler
DCD IRQ069_Handler ; IRQ069_Handler
DCD IRQ070_Handler ; IRQ070_Handler
DCD IRQ071_Handler ; IRQ071_Handler
DCD IRQ072_Handler ; IRQ072_Handler
DCD IRQ073_Handler ; IRQ073_Handler
DCD IRQ074_Handler ; IRQ074_Handler
DCD IRQ075_Handler ; IRQ075_Handler
DCD IRQ076_Handler ; IRQ076_Handler
DCD IRQ077_Handler ; IRQ077_Handler
DCD IRQ078_Handler ; IRQ078_Handler
DCD IRQ079_Handler ; IRQ079_Handler
DCD IRQ080_Handler ; IRQ080_Handler
DCD IRQ081_Handler ; IRQ081_Handler
DCD IRQ082_Handler ; IRQ082_Handler
DCD IRQ083_Handler ; IRQ083_Handler
DCD IRQ084_Handler ; IRQ084_Handler
DCD IRQ085_Handler ; IRQ085_Handler
DCD IRQ086_Handler ; IRQ086_Handler
DCD IRQ087_Handler ; IRQ087_Handler
DCD IRQ088_Handler ; IRQ088_Handler
DCD IRQ089_Handler ; IRQ089_Handler
DCD IRQ090_Handler ; IRQ090_Handler
DCD IRQ091_Handler ; IRQ091_Handler
DCD IRQ092_Handler ; IRQ092_Handler
DCD IRQ093_Handler ; IRQ093_Handler
DCD IRQ094_Handler ; IRQ094_Handler
DCD IRQ095_Handler ; IRQ095_Handler
DCD IRQ096_Handler ; IRQ096_Handler
DCD IRQ097_Handler ; IRQ097_Handler
DCD IRQ098_Handler ; IRQ098_Handler
DCD IRQ099_Handler ; IRQ099_Handler
DCD IRQ100_Handler ; IRQ100_Handler
DCD IRQ101_Handler ; IRQ101_Handler
DCD IRQ102_Handler ; IRQ102_Handler
DCD IRQ103_Handler ; IRQ103_Handler
DCD IRQ104_Handler ; IRQ104_Handler
DCD IRQ105_Handler ; IRQ105_Handler
DCD IRQ106_Handler ; IRQ106_Handler
DCD IRQ107_Handler ; IRQ107_Handler
DCD IRQ108_Handler ; IRQ108_Handler
DCD IRQ109_Handler ; IRQ109_Handler
DCD IRQ110_Handler ; IRQ110_Handler
DCD IRQ111_Handler ; IRQ111_Handler
DCD IRQ112_Handler ; IRQ112_Handler
DCD IRQ113_Handler ; IRQ113_Handler
DCD IRQ114_Handler ; IRQ114_Handler
DCD IRQ115_Handler ; IRQ115_Handler
DCD IRQ116_Handler ; IRQ116_Handler
DCD IRQ117_Handler ; IRQ117_Handler
DCD IRQ118_Handler ; IRQ118_Handler
DCD IRQ119_Handler ; IRQ119_Handler
DCD IRQ120_Handler ; IRQ120_Handler
DCD IRQ121_Handler ; IRQ121_Handler
DCD IRQ122_Handler ; IRQ122_Handler
DCD IRQ123_Handler ; IRQ123_Handler
DCD IRQ124_Handler ; IRQ124_Handler
DCD IRQ125_Handler ; IRQ125_Handler
DCD IRQ126_Handler ; IRQ126_Handler
DCD IRQ127_Handler ; IRQ127_Handler
DCD IRQ128_Handler ; IRQ128_Handler
DCD IRQ129_Handler ; IRQ129_Handler
DCD IRQ130_Handler ; IRQ130_Handler
DCD IRQ131_Handler ; IRQ131_Handler
DCD IRQ132_Handler ; IRQ132_Handler
DCD IRQ133_Handler ; IRQ133_Handler
DCD IRQ134_Handler ; IRQ134_Handler
DCD IRQ135_Handler ; IRQ135_Handler
DCD IRQ136_Handler ; IRQ136_Handler
DCD IRQ137_Handler ; IRQ137_Handler
DCD IRQ138_Handler ; IRQ138_Handler
DCD IRQ139_Handler ; IRQ139_Handler
DCD IRQ140_Handler ; IRQ140_Handler
DCD IRQ141_Handler ; IRQ141_Handler
DCD IRQ142_Handler ; IRQ142_Handler
DCD IRQ143_Handler ; IRQ143_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
SET_SRAM3_WAIT
LDR R0, =0x40050804
MOV R1, #0x77
STR R1, [R0]
LDR R0, =0x4005080C
MOV R1, #0x77
STR R1, [R0]
LDR R0, =0x40050800
MOV R1, #0x1100
STR R1, [R0]
LDR R0, =0x40050804
MOV R1, #0x76
STR R1, [R0]
LDR R0, =0x4005080C
MOV R1, #0x76
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT IRQ000_Handler [WEAK]
EXPORT IRQ001_Handler [WEAK]
EXPORT IRQ002_Handler [WEAK]
EXPORT IRQ003_Handler [WEAK]
EXPORT IRQ004_Handler [WEAK]
EXPORT IRQ005_Handler [WEAK]
EXPORT IRQ006_Handler [WEAK]
EXPORT IRQ007_Handler [WEAK]
EXPORT IRQ008_Handler [WEAK]
EXPORT IRQ009_Handler [WEAK]
EXPORT IRQ010_Handler [WEAK]
EXPORT IRQ011_Handler [WEAK]
EXPORT IRQ012_Handler [WEAK]
EXPORT IRQ013_Handler [WEAK]
EXPORT IRQ014_Handler [WEAK]
EXPORT IRQ015_Handler [WEAK]
EXPORT IRQ016_Handler [WEAK]
EXPORT IRQ017_Handler [WEAK]
EXPORT IRQ018_Handler [WEAK]
EXPORT IRQ019_Handler [WEAK]
EXPORT IRQ020_Handler [WEAK]
EXPORT IRQ021_Handler [WEAK]
EXPORT IRQ022_Handler [WEAK]
EXPORT IRQ023_Handler [WEAK]
EXPORT IRQ024_Handler [WEAK]
EXPORT IRQ025_Handler [WEAK]
EXPORT IRQ026_Handler [WEAK]
EXPORT IRQ027_Handler [WEAK]
EXPORT IRQ028_Handler [WEAK]
EXPORT IRQ029_Handler [WEAK]
EXPORT IRQ030_Handler [WEAK]
EXPORT IRQ031_Handler [WEAK]
EXPORT IRQ032_Handler [WEAK]
EXPORT IRQ033_Handler [WEAK]
EXPORT IRQ034_Handler [WEAK]
EXPORT IRQ035_Handler [WEAK]
EXPORT IRQ036_Handler [WEAK]
EXPORT IRQ037_Handler [WEAK]
EXPORT IRQ038_Handler [WEAK]
EXPORT IRQ039_Handler [WEAK]
EXPORT IRQ040_Handler [WEAK]
EXPORT IRQ041_Handler [WEAK]
EXPORT IRQ042_Handler [WEAK]
EXPORT IRQ043_Handler [WEAK]
EXPORT IRQ044_Handler [WEAK]
EXPORT IRQ045_Handler [WEAK]
EXPORT IRQ046_Handler [WEAK]
EXPORT IRQ047_Handler [WEAK]
EXPORT IRQ048_Handler [WEAK]
EXPORT IRQ049_Handler [WEAK]
EXPORT IRQ050_Handler [WEAK]
EXPORT IRQ051_Handler [WEAK]
EXPORT IRQ052_Handler [WEAK]
EXPORT IRQ053_Handler [WEAK]
EXPORT IRQ054_Handler [WEAK]
EXPORT IRQ055_Handler [WEAK]
EXPORT IRQ056_Handler [WEAK]
EXPORT IRQ057_Handler [WEAK]
EXPORT IRQ058_Handler [WEAK]
EXPORT IRQ059_Handler [WEAK]
EXPORT IRQ060_Handler [WEAK]
EXPORT IRQ061_Handler [WEAK]
EXPORT IRQ062_Handler [WEAK]
EXPORT IRQ063_Handler [WEAK]
EXPORT IRQ064_Handler [WEAK]
EXPORT IRQ065_Handler [WEAK]
EXPORT IRQ066_Handler [WEAK]
EXPORT IRQ067_Handler [WEAK]
EXPORT IRQ068_Handler [WEAK]
EXPORT IRQ069_Handler [WEAK]
EXPORT IRQ070_Handler [WEAK]
EXPORT IRQ071_Handler [WEAK]
EXPORT IRQ072_Handler [WEAK]
EXPORT IRQ073_Handler [WEAK]
EXPORT IRQ074_Handler [WEAK]
EXPORT IRQ075_Handler [WEAK]
EXPORT IRQ076_Handler [WEAK]
EXPORT IRQ077_Handler [WEAK]
EXPORT IRQ078_Handler [WEAK]
EXPORT IRQ079_Handler [WEAK]
EXPORT IRQ080_Handler [WEAK]
EXPORT IRQ081_Handler [WEAK]
EXPORT IRQ082_Handler [WEAK]
EXPORT IRQ083_Handler [WEAK]
EXPORT IRQ084_Handler [WEAK]
EXPORT IRQ085_Handler [WEAK]
EXPORT IRQ086_Handler [WEAK]
EXPORT IRQ087_Handler [WEAK]
EXPORT IRQ088_Handler [WEAK]
EXPORT IRQ089_Handler [WEAK]
EXPORT IRQ090_Handler [WEAK]
EXPORT IRQ091_Handler [WEAK]
EXPORT IRQ092_Handler [WEAK]
EXPORT IRQ093_Handler [WEAK]
EXPORT IRQ094_Handler [WEAK]
EXPORT IRQ095_Handler [WEAK]
EXPORT IRQ096_Handler [WEAK]
EXPORT IRQ097_Handler [WEAK]
EXPORT IRQ098_Handler [WEAK]
EXPORT IRQ099_Handler [WEAK]
EXPORT IRQ100_Handler [WEAK]
EXPORT IRQ101_Handler [WEAK]
EXPORT IRQ102_Handler [WEAK]
EXPORT IRQ103_Handler [WEAK]
EXPORT IRQ104_Handler [WEAK]
EXPORT IRQ105_Handler [WEAK]
EXPORT IRQ106_Handler [WEAK]
EXPORT IRQ107_Handler [WEAK]
EXPORT IRQ108_Handler [WEAK]
EXPORT IRQ109_Handler [WEAK]
EXPORT IRQ110_Handler [WEAK]
EXPORT IRQ111_Handler [WEAK]
EXPORT IRQ112_Handler [WEAK]
EXPORT IRQ113_Handler [WEAK]
EXPORT IRQ114_Handler [WEAK]
EXPORT IRQ115_Handler [WEAK]
EXPORT IRQ116_Handler [WEAK]
EXPORT IRQ117_Handler [WEAK]
EXPORT IRQ118_Handler [WEAK]
EXPORT IRQ119_Handler [WEAK]
EXPORT IRQ120_Handler [WEAK]
EXPORT IRQ121_Handler [WEAK]
EXPORT IRQ122_Handler [WEAK]
EXPORT IRQ123_Handler [WEAK]
EXPORT IRQ124_Handler [WEAK]
EXPORT IRQ125_Handler [WEAK]
EXPORT IRQ126_Handler [WEAK]
EXPORT IRQ127_Handler [WEAK]
EXPORT IRQ128_Handler [WEAK]
EXPORT IRQ129_Handler [WEAK]
EXPORT IRQ130_Handler [WEAK]
EXPORT IRQ131_Handler [WEAK]
EXPORT IRQ132_Handler [WEAK]
EXPORT IRQ133_Handler [WEAK]
EXPORT IRQ134_Handler [WEAK]
EXPORT IRQ135_Handler [WEAK]
EXPORT IRQ136_Handler [WEAK]
EXPORT IRQ137_Handler [WEAK]
EXPORT IRQ138_Handler [WEAK]
EXPORT IRQ139_Handler [WEAK]
EXPORT IRQ140_Handler [WEAK]
EXPORT IRQ141_Handler [WEAK]
EXPORT IRQ142_Handler [WEAK]
EXPORT IRQ143_Handler [WEAK]
IRQ000_Handler
IRQ001_Handler
IRQ002_Handler
IRQ003_Handler
IRQ004_Handler
IRQ005_Handler
IRQ006_Handler
IRQ007_Handler
IRQ008_Handler
IRQ009_Handler
IRQ010_Handler
IRQ011_Handler
IRQ012_Handler
IRQ013_Handler
IRQ014_Handler
IRQ015_Handler
IRQ016_Handler
IRQ017_Handler
IRQ018_Handler
IRQ019_Handler
IRQ020_Handler
IRQ021_Handler
IRQ022_Handler
IRQ023_Handler
IRQ024_Handler
IRQ025_Handler
IRQ026_Handler
IRQ027_Handler
IRQ028_Handler
IRQ029_Handler
IRQ030_Handler
IRQ031_Handler
IRQ032_Handler
IRQ033_Handler
IRQ034_Handler
IRQ035_Handler
IRQ036_Handler
IRQ037_Handler
IRQ038_Handler
IRQ039_Handler
IRQ040_Handler
IRQ041_Handler
IRQ042_Handler
IRQ043_Handler
IRQ044_Handler
IRQ045_Handler
IRQ046_Handler
IRQ047_Handler
IRQ048_Handler
IRQ049_Handler
IRQ050_Handler
IRQ051_Handler
IRQ052_Handler
IRQ053_Handler
IRQ054_Handler
IRQ055_Handler
IRQ056_Handler
IRQ057_Handler
IRQ058_Handler
IRQ059_Handler
IRQ060_Handler
IRQ061_Handler
IRQ062_Handler
IRQ063_Handler
IRQ064_Handler
IRQ065_Handler
IRQ066_Handler
IRQ067_Handler
IRQ068_Handler
IRQ069_Handler
IRQ070_Handler
IRQ071_Handler
IRQ072_Handler
IRQ073_Handler
IRQ074_Handler
IRQ075_Handler
IRQ076_Handler
IRQ077_Handler
IRQ078_Handler
IRQ079_Handler
IRQ080_Handler
IRQ081_Handler
IRQ082_Handler
IRQ083_Handler
IRQ084_Handler
IRQ085_Handler
IRQ086_Handler
IRQ087_Handler
IRQ088_Handler
IRQ089_Handler
IRQ090_Handler
IRQ091_Handler
IRQ092_Handler
IRQ093_Handler
IRQ094_Handler
IRQ095_Handler
IRQ096_Handler
IRQ097_Handler
IRQ098_Handler
IRQ099_Handler
IRQ100_Handler
IRQ101_Handler
IRQ102_Handler
IRQ103_Handler
IRQ104_Handler
IRQ105_Handler
IRQ106_Handler
IRQ107_Handler
IRQ108_Handler
IRQ109_Handler
IRQ110_Handler
IRQ111_Handler
IRQ112_Handler
IRQ113_Handler
IRQ114_Handler
IRQ115_Handler
IRQ116_Handler
IRQ117_Handler
IRQ118_Handler
IRQ119_Handler
IRQ120_Handler
IRQ121_Handler
IRQ122_Handler
IRQ123_Handler
IRQ124_Handler
IRQ125_Handler
IRQ126_Handler
IRQ127_Handler
IRQ128_Handler
IRQ129_Handler
IRQ130_Handler
IRQ131_Handler
IRQ132_Handler
IRQ133_Handler
IRQ134_Handler
IRQ135_Handler
IRQ136_Handler
IRQ137_Handler
IRQ138_Handler
IRQ139_Handler
IRQ140_Handler
IRQ141_Handler
IRQ142_Handler
IRQ143_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

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================================================================================
样例使用说明
================================================================================
版本历史
日期 版本 负责人 IAR MDK GCC 描述
2018-11-27 1.0 Husj 7.70 5.16 8.3.1 first version
================================================================================
平台说明
================================================================================
GCC工程,由Eclipse IDE外挂GNU-ARM Toolchain,再结合pyOCD GDB Server实现工程的编译、
链接和调试。在用Eclipse导入工程后,请将xxxx_PyOCDDebug中pyocd-gdbserver和SVD文件
设置为正确的路径;请将xxxx_PyOCDDownload中pyocd设置为正确的路径。注意,这些路径不
能包含非英文字符。
功能描述
================================================================================
本样例主要展示MCU的TIMER6的AB相位置编码计数功能(1倍和2倍计数)
说明:
配置timer6,hclk设置为168M
LED0:PE06
LED1:PD07
LED0和LED1引脚模拟位置信号,分别输入到PWMA和PWMB引脚
================================================================================
测试环境
================================================================================
测试用板:
---------------------
EV-HC32F460-LQFP100-050-V1.1
辅助工具:
---------------------
示波器
辅助软件:
---------------------
无
================================================================================
使用步骤
================================================================================
1) 连接PE06与PE09,PD07与PE08
2) 打开工程编译并全速运行。
3) 在寄存器窗口或者livewatch观察u16Timer6Cnt0的值,当PE06与PD07输出不同信号组合的时候
Timer61的CNTER自增或自减计数。
================================================================================
注意
================================================================================
================================================================================

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/*******************************************************************************
* Copyright (C) 2016, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software is owned and published by:
* Huada Semiconductor Co., Ltd. ("HDSC").
*
* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
*
* This software contains source code for use with HDSC
* components. This software is licensed by HDSC to be adapted only
* for use in systems utilizing HDSC components. HDSC shall not be
* responsible for misuse or illegal use of this software for devices not
* supported herein. HDSC is providing this software "AS IS" and will
* not be responsible for issues arising from incorrect user implementation
* of the software.
*
* Disclaimer:
* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
* REGARDING THE SOFTWARE (INCLUDING ANY ACCOMPANYING WRITTEN MATERIALS),
* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
* WARRANTY OF NONINFRINGEMENT.
* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
* SAVINGS OR PROFITS,
* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
* FROM, THE SOFTWARE.
*
* This software may be replicated in part or whole for the licensed use,
* with the restriction that this Disclaimer and Copyright notice must be
* included with each copy of this software, whether used in part or whole,
* at all times.
*/
/******************************************************************************/
/** \file ddl_config.h
**
** A detailed description is available at
** @link DdlConfigGroup Ddl Config description @endlink
**
** - 2018-10-18 1.0 Yangjp First version for Device Driver Library config.
**
******************************************************************************/
#ifndef __DDL_CONFIG_H__
#define __DDL_CONFIG_H__
/*******************************************************************************
* Include files
******************************************************************************/
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/**
*******************************************************************************
** \defgroup DdlConfigGroup Device Driver Library config(DDLCONFIG)
**
******************************************************************************/
//@{
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*! Chip module on-off define */
#define DDL_ON (1u)
#define DDL_OFF (0u)
/**
*******************************************************************************
** \brief This is the list of modules to be used in the device driver library
** Select the modules you need to use to DDL_ON.
**
** \note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
** properly.
**
** \note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
** Library.
******************************************************************************/
#define DDL_ICG_ENABLE (DDL_ON)
#define DDL_UTILITY_ENABLE (DDL_ON)
#define DDL_ADC_ENABLE (DDL_OFF)
#define DDL_AES_ENABLE (DDL_OFF)
#define DDL_CAN_ENABLE (DDL_OFF)
#define DDL_CLK_ENABLE (DDL_ON)
#define DDL_CMP_ENABLE (DDL_OFF)
#define DDL_CRC_ENABLE (DDL_OFF)
#define DDL_DCU_ENABLE (DDL_OFF)
#define DDL_DMAC_ENABLE (DDL_OFF)
#define DDL_EFM_ENABLE (DDL_ON)
#define DDL_EMB_ENABLE (DDL_OFF)
#define DDL_EVENT_PORT_ENABLE (DDL_OFF)
#define DDL_EXINT_NMI_SWI_ENABLE (DDL_OFF)
#define DDL_GPIO_ENABLE (DDL_ON)
#define DDL_HASH_ENABLE (DDL_OFF)
#define DDL_I2C_ENABLE (DDL_OFF)
#define DDL_I2S_ENABLE (DDL_OFF)
#define DDL_INTERRUPTS_ENABLE (DDL_ON)
#define DDL_KEYSCAN_ENABLE (DDL_OFF)
#define DDL_MPU_ENABLE (DDL_OFF)
#define DDL_OTS_ENABLE (DDL_OFF)
#define DDL_PWC_ENABLE (DDL_ON)
#define DDL_QSPI_ENABLE (DDL_OFF)
#define DDL_RMU_ENABLE (DDL_OFF)
#define DDL_RTC_ENABLE (DDL_OFF)
#define DDL_SDIOC_ENABLE (DDL_OFF)
#define DDL_SPI_ENABLE (DDL_OFF)
#define DDL_SRAM_ENABLE (DDL_OFF)
#define DDL_SWDT_ENABLE (DDL_OFF)
#define DDL_TIMER0_ENABLE (DDL_OFF)
#define DDL_TIMER4_CNT_ENABLE (DDL_OFF)
#define DDL_TIMER4_EMB_ENABLE (DDL_OFF)
#define DDL_TIMER4_OCO_ENABLE (DDL_OFF)
#define DDL_TIMER4_PWM_ENABLE (DDL_OFF)
#define DDL_TIMER4_SEVT_ENABLE (DDL_OFF)
#define DDL_TIMER6_ENABLE (DDL_ON)
#define DDL_TIMERA_ENABLE (DDL_OFF)
#define DDL_TRNG_ENABLE (DDL_OFF)
#define DDL_USART_ENABLE (DDL_OFF)
#define DDL_USBFS_ENABLE (DDL_OFF)
#define DDL_WDT_ENABLE (DDL_OFF)
/*! Midware module on-off define */
#define MW_ON (1u)
#define MW_OFF (0u)
/**
*******************************************************************************
** \brief This is the list of Midware modules to use
** Select the modules you need to use to MW_ON.
******************************************************************************/
#define MW_SD_CARD_ENABLE (MW_OFF)
#define MW_FS_ENABLE (MW_OFF)
#define MW_W25QXX_ENABLE (MW_OFF)
#define MW_WM8731_ENABLE (MW_OFF)
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
//@} // DdlConfigGroup
#ifdef __cplusplus
}
#endif
#endif /* __DDL_CONFIG_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/*******************************************************************************
* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
*
* This software is owned and published by:
* Huada Semiconductor Co.,Ltd ("HDSC").
*
* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
*
* This software contains source code for use with HDSC
* components. This software is licensed by HDSC to be adapted only
* for use in systems utilizing HDSC components. HDSC shall not be
* responsible for misuse or illegal use of this software for devices not
* supported herein. HDSC is providing this software "AS IS" and will
* not be responsible for issues arising from incorrect user implementation
* of the software.
*
* Disclaimer:
* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
* REGARDING THE SOFTWARE (INCLUDING ANY ACCOMPANYING WRITTEN MATERIALS),
* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
* WARRANTY OF NONINFRINGEMENT.
* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
* SAVINGS OR PROFITS,
* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
* FROM, THE SOFTWARE.
*
* This software may be replicated in part or whole for the licensed use,
* with the restriction that this Disclaimer and Copyright notice must be
* included with each copy of this software, whether used in part or whole,
* at all times.
*/
/******************************************************************************/
/** \file main.c
**
** \brief This sample demonstrates how to use Timer6.
**
** - 2018-11-30 1.0 husj first version for Device Driver Library of Timer6.
**
******************************************************************************/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_ddl.h"
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/* KEY0 (SW2)*/
#define SW2_PORT (PortD)
#define SW2_PIN (Pin03)
/* KEY1 (SW4)*/
#define SW4_PORT (PortD)
#define SW4_PIN (Pin04)
/* KEY2 (SW3)*/
#define SW3_PORT (PortD)
#define SW3_PIN (Pin05)
/* KEY3 (SW5)*/
#define SW5_PORT (PortD)
#define SW5_PIN (Pin06)
/* LED0 Port/Pin definition */
#define LED0_PORT (PortE)
#define LED0_PIN (Pin06)
/* LED1 Port/Pin definition */
#define LED1_PORT (PortD)
#define LED1_PIN (Pin07)
/* LED2 Port/Pin definition */
#define LED2_PORT (PortB)
#define LED2_PIN (Pin05)
/* LED3 Port/Pin definition */
#define LED3_PORT (PortB)
#define LED3_PIN (Pin09)
/* LED0~1 toggle definition */
#define LED0_TOGGLE() (PORT_Toggle(LED0_PORT, LED0_PIN))
#define LED1_TOGGLE() (PORT_Toggle(LED1_PORT, LED1_PIN))
#define LED2_TOGGLE() (PORT_Toggle(LED2_PORT, LED2_PIN))
#define LED3_TOGGLE() (PORT_Toggle(LED3_PORT, LED3_PIN))
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
//uint16_t u16Timer6Cnt0 = 0u;
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
static volatile uint16_t u16Timer6Cnt0 = 0u;
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
*******************************************************************************
** \brief Callback function of external interrupt ch.0
**
******************************************************************************/
void Timer6_OverFlow_CallBack(void)
{
}
/**
******************************************************************************
** \brief Initialize the system clock for the sample
**
** \param None
**
** \return None
******************************************************************************/
static void SysClkIni(void)
{
en_clk_sys_source_t enSysClkSrc;
stc_clk_sysclk_cfg_t stcSysClkCfg;
stc_clk_mpll_cfg_t stcMpllCfg;
MEM_ZERO_STRUCT(enSysClkSrc);
MEM_ZERO_STRUCT(stcSysClkCfg);
MEM_ZERO_STRUCT(stcMpllCfg);
/* Set bus clk div. */
stcSysClkCfg.enHclkDiv = ClkSysclkDiv1; // 168MHz
stcSysClkCfg.enExclkDiv = ClkSysclkDiv2; // 84MHz
stcSysClkCfg.enPclk0Div = ClkSysclkDiv1; // 168MHz
stcSysClkCfg.enPclk1Div = ClkSysclkDiv2; // 84MHz
stcSysClkCfg.enPclk2Div = ClkSysclkDiv4; // 42MHz
stcSysClkCfg.enPclk3Div = ClkSysclkDiv4; // 42MHz
stcSysClkCfg.enPclk4Div = ClkSysclkDiv2; // 84MHz
CLK_SysClkConfig(&stcSysClkCfg);
CLK_HrcCmd(Enable); //Enable HRC
/* MPLL config. */
stcMpllCfg.pllmDiv = 2ul; //HRC 16M / 2
stcMpllCfg.plln = 42ul; //8M*42 = 336M
stcMpllCfg.PllpDiv = 2ul; //MLLP = 168M
stcMpllCfg.PllqDiv = 2ul; //MLLQ = 168M
stcMpllCfg.PllrDiv = 2ul; //MLLR = 168M
CLK_SetPllSource(ClkPllSrcHRC);
CLK_MpllConfig(&stcMpllCfg);
/* flash read wait cycle setting */
EFM_Unlock();
EFM_SetLatency(EFM_LATENCY_4);
EFM_Lock();
/* Enable MPLL. */
CLK_MpllCmd(Enable);
/* Wait MPLL ready. */
while(Set != CLK_GetFlagStatus(ClkFlagMPLLRdy))
{
;
}
/* Switch system clock source to MPLL. */
CLK_SetSysClkSource(CLKSysSrcMPLL);
}
static void genClkIn(void)
{
uint32_t i;
uint8_t bAin[17] = {0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1};
uint8_t bBin[17] = {1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1};
for (i = 0ul; i < 17ul; i++)
{
u16Timer6Cnt0 = Timer6_GetCount(M4_TMR61);//M4_TMR61->CNTER;
M4_PORT->PODRE_f.POUT06 = bAin[i];
M4_PORT->PODRD_f.POUT07 = bBin[i];
Ddl_Delay1ms(1000ul);
}
u16Timer6Cnt0 = Timer6_GetCount(M4_TMR61);//M4_TMR60->CNTER;
}
/**
*******************************************************************************
** \brief Main function of project
**
** \param None
**
** \retval int32_t return value, if needed
**
******************************************************************************/
int32_t main(void)
{
stc_timer6_basecnt_cfg_t stcTIM6BaseCntCfg;
stc_port_init_t stcPortInit;
stc_irq_regi_conf_t stcIrqRegiConf;
stc_timer6_port_input_cfg_t stcPortInputCfg;
MEM_ZERO_STRUCT(stcTIM6BaseCntCfg);
MEM_ZERO_STRUCT(stcPortInit);
MEM_ZERO_STRUCT(stcIrqRegiConf);
MEM_ZERO_STRUCT(stcPortInputCfg);
SysClkIni();
PWC_Fcg2PeriphClockCmd(PWC_FCG2_PERIPH_TIM61, Enable);
/*initiallize LED port*/
stcPortInit.enPinMode = Pin_Mode_Out;
stcPortInit.enPullUp = Enable;
/* LED0 and LED1 Port/Pin initialization */
PORT_Init(LED0_PORT, LED0_PIN, &stcPortInit); //LED0 --> PWMA
PORT_Init(LED1_PORT, LED1_PIN, &stcPortInit); //LED1 --> PWMB
//PORT_Init(LED2_PORT, LED2_PIN, &stcPortInit);
M4_PORT->PODRE_f.POUT06 = 0u;
M4_PORT->PODRD_f.POUT07 = 0u;
PORT_SetFunc(PortE, Pin09, Func_Tim6, Disable); //Timer61 PWMA
PORT_SetFunc(PortE, Pin08, Func_Tim6, Disable); //Timer61 PWMB
stcTIM6BaseCntCfg.enCntMode = Timer6CntSawtoothMode; //Sawtooth wave mode
stcTIM6BaseCntCfg.enCntDir = Timer6CntDirUp; //Counter counting up
stcTIM6BaseCntCfg.enCntClkDiv = Timer6PclkDiv1; //Count clock: pclk
Timer6_Init(M4_TMR61, &stcTIM6BaseCntCfg); //timer6 PWM frequency, count mode and clk config
stcPortInputCfg.enPortSel = Timer6xCHA; //Capture Input Port: PWM A port
stcPortInputCfg.enPortMode = Timer6ModeCaptureInput; //Capture input function
stcPortInputCfg.bFltEn = true; //Input filter enable
stcPortInputCfg.enFltClk = Timer6FltClkPclk0Div64; //Filter clock
Timer6_PortInputConfig(M4_TMR61, &stcPortInputCfg); //Input config
stcPortInputCfg.enPortSel = Timer6xCHB; //Capture Input Port: PWM A port
stcPortInputCfg.enPortMode = Timer6ModeCaptureInput; //Capture input function
stcPortInputCfg.bFltEn = true; //Input filter enable
stcPortInputCfg.enFltClk = Timer6FltClkPclk0Div64; //Filter clock
Timer6_PortInputConfig(M4_TMR61, &stcPortInputCfg); //Input config
while(1)
{
M4_PORT->PODRE_f.POUT06 = 0u;
M4_PORT->PODRD_f.POUT07 = 1u;
Ddl_Delay1ms(1000ul);
Timer6_ClearHwCntUp(M4_TMR61);
Timer6_ClearHwCntDwn(M4_TMR61);
Timer6_ConfigHwCntUp(M4_TMR61, Timer6HwCntPWMBHighPWMARise); // PWMA Rising trigger when PWMB is high level
Timer6_ConfigHwCntDwn(M4_TMR61, Timer6HwCntPWMBLowPWMARise); // PWMA Rising trigger when PWMB is low level
//Timer6_SetCount(M4_TMR61, 3);
Timer6_StartCount(M4_TMR61);
genClkIn();
Timer6_StopCount(M4_TMR61);
Timer6_ClearCount(M4_TMR61);
M4_PORT->PODRE_f.POUT06 = 0u;
M4_PORT->PODRD_f.POUT07 = 1u;
Ddl_Delay1ms(2000ul);
Timer6_ClearHwCntUp(M4_TMR61);
Timer6_ClearHwCntDwn(M4_TMR61);
Timer6_ConfigHwCntUp(M4_TMR61, Timer6HwCntPWMBHighPWMARise); // PWMA Rising trigger when PWMB is high level
Timer6_ConfigHwCntUp(M4_TMR61, Timer6HwCntPWMBLowPWMAFall); // PWMA falling trigger when PWMB is low level
Timer6_ConfigHwCntDwn(M4_TMR61, Timer6HwCntPWMAHighPWMBRise); // PWMB Rising trigger when PWMA is high level
Timer6_ConfigHwCntDwn(M4_TMR61, Timer6HwCntPWMALowPWMBFall); // PWMB falling trigger when PWMA is low level
//Timer6_SetCount(M4_TMR61, 3);
Timer6_StartCount(M4_TMR61);
genClkIn();
Timer6_StopCount(M4_TMR61);
Timer6_ClearCount(M4_TMR61);
}
}
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/